WO2011109487A8 - Method and apparatus for testing a memory device - Google Patents
Method and apparatus for testing a memory device Download PDFInfo
- Publication number
- WO2011109487A8 WO2011109487A8 PCT/US2011/026826 US2011026826W WO2011109487A8 WO 2011109487 A8 WO2011109487 A8 WO 2011109487A8 US 2011026826 W US2011026826 W US 2011026826W WO 2011109487 A8 WO2011109487 A8 WO 2011109487A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- testing
- semiconductor device
- memory device
- controller
- well
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
Abstract
In a particular embodiment, a method includes receiving a testing activation signal (138) at a controller (108) coupled to a semiconductor device (104). The method further includes biasing a well (142) of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit (106) that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/716,341 | 2010-03-03 | ||
US12/716,341 US8466707B2 (en) | 2010-03-03 | 2010-03-03 | Method and apparatus for testing a memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2011109487A1 WO2011109487A1 (en) | 2011-09-09 |
WO2011109487A8 true WO2011109487A8 (en) | 2011-10-27 |
Family
ID=44140936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2011/026826 WO2011109487A1 (en) | 2010-03-03 | 2011-03-02 | Method and apparatus for testing a memory device |
Country Status (3)
Country | Link |
---|---|
US (2) | US8466707B2 (en) |
TW (1) | TW201218201A (en) |
WO (1) | WO2011109487A1 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8466707B2 (en) * | 2010-03-03 | 2013-06-18 | Qualcomm Incorporated | Method and apparatus for testing a memory device |
US8823385B2 (en) * | 2011-03-10 | 2014-09-02 | Infineon Technologies Ag | Detection of pre-catastrophic, stress induced leakage current conditions for dielectric layers |
US8575993B2 (en) | 2011-08-17 | 2013-11-05 | Broadcom Corporation | Integrated circuit with pre-heating for reduced subthreshold leakage |
US9613691B2 (en) * | 2015-03-27 | 2017-04-04 | Intel Corporation | Apparatus and method for drift cancellation in a memory |
KR20170013577A (en) * | 2015-07-28 | 2017-02-07 | 에스케이하이닉스 주식회사 | Semiconductor device |
US9824767B1 (en) | 2016-06-29 | 2017-11-21 | Intel Corporation | Methods and apparatus to reduce threshold voltage drift |
CN110672943B (en) * | 2019-09-26 | 2022-11-08 | 宁波大学 | Aging detection sensor based on voltage comparator |
US11099229B2 (en) * | 2020-01-10 | 2021-08-24 | Cisco Technology, Inc. | Connectivity verification for flip-chip and advanced packaging technologies |
CN113760194B (en) * | 2021-09-09 | 2024-03-12 | 合肥兆芯电子有限公司 | Memory temperature control method and memory temperature control system |
CN116148549A (en) * | 2021-11-19 | 2023-05-23 | 英业达科技有限公司 | System and method for testing radiation sensitivity |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2308820A1 (en) * | 2000-05-15 | 2001-11-15 | The Governors Of The University Of Alberta | Wireless radio frequency technique design and method for testing of integrated circuits and wafers |
US6815970B2 (en) | 2001-08-31 | 2004-11-09 | Texas Instruments Incorporated | Method for measuring NBTI degradation effects on integrated circuits |
US6731179B2 (en) | 2002-04-09 | 2004-05-04 | International Business Machines Corporation | System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI) |
US6989698B2 (en) * | 2002-08-26 | 2006-01-24 | Integrant Technologies Inc. | Charge pump circuit for compensating mismatch of output currents |
US7177201B1 (en) | 2003-09-17 | 2007-02-13 | Sun Microsystems, Inc. | Negative bias temperature instability (NBTI) preconditioning of matched devices |
US6900656B1 (en) * | 2003-11-10 | 2005-05-31 | Texas Instruments Incorporated | Method of testing an integrated circuit and an integrated circuit test apparatus |
US7183791B2 (en) * | 2004-10-11 | 2007-02-27 | Lsi Logic Corporation | Reliability circuit for applying an AC stress signal or DC measurement to a transistor device |
US20060267621A1 (en) * | 2005-05-27 | 2006-11-30 | Harris Edward B | On-chip apparatus and method for determining integrated circuit stress conditions |
JP2007157287A (en) | 2005-12-07 | 2007-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor storage device |
JP4996215B2 (en) * | 2006-11-28 | 2012-08-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device test method |
US7665003B2 (en) * | 2006-12-15 | 2010-02-16 | Qualcomm Incorporated | Method and device for testing memory |
US7859340B2 (en) * | 2007-03-30 | 2010-12-28 | Qualcomm Incorporated | Metal-oxide-semiconductor circuit designs and methods for operating same |
US7827018B2 (en) | 2007-11-16 | 2010-11-02 | International Business Machines Corporation | Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects |
US7642864B2 (en) * | 2008-01-29 | 2010-01-05 | International Business Machines Corporation | Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect |
US7872930B2 (en) * | 2008-05-15 | 2011-01-18 | Qualcomm, Incorporated | Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability |
US8466707B2 (en) * | 2010-03-03 | 2013-06-18 | Qualcomm Incorporated | Method and apparatus for testing a memory device |
US8659322B2 (en) * | 2011-01-28 | 2014-02-25 | Freescale Semiconductor, Inc. | Memory having a latching sense amplifier resistant to negative bias temperature instability and method therefor |
-
2010
- 2010-03-03 US US12/716,341 patent/US8466707B2/en not_active Expired - Fee Related
-
2011
- 2011-03-02 WO PCT/US2011/026826 patent/WO2011109487A1/en active Application Filing
- 2011-03-03 TW TW100107220A patent/TW201218201A/en unknown
-
2013
- 2013-05-23 US US13/900,775 patent/US8884637B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20110215827A1 (en) | 2011-09-08 |
US8466707B2 (en) | 2013-06-18 |
US8884637B2 (en) | 2014-11-11 |
US20130257466A1 (en) | 2013-10-03 |
TW201218201A (en) | 2012-05-01 |
WO2011109487A1 (en) | 2011-09-09 |
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