WO2004025661A3 - Static random access memory with symmetric leakage-compensated bit line - Google Patents

Static random access memory with symmetric leakage-compensated bit line Download PDF

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Publication number
WO2004025661A3
WO2004025661A3 PCT/US2003/027789 US0327789W WO2004025661A3 WO 2004025661 A3 WO2004025661 A3 WO 2004025661A3 US 0327789 W US0327789 W US 0327789W WO 2004025661 A3 WO2004025661 A3 WO 2004025661A3
Authority
WO
WIPO (PCT)
Prior art keywords
random access
static random
access memory
bit line
compensated bit
Prior art date
Application number
PCT/US2003/027789
Other languages
French (fr)
Other versions
WO2004025661A2 (en
Inventor
Atila Alvandpour
Dinesh Somasekhar
Steven Hsu
Ram Krishnamurty
Vivek De
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AU2003273284A priority Critical patent/AU2003273284A1/en
Publication of WO2004025661A2 publication Critical patent/WO2004025661A2/en
Publication of WO2004025661A3 publication Critical patent/WO2004025661A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Abstract

An eight-cell memory cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.
PCT/US2003/027789 2002-09-10 2003-09-05 Static random access memory with symmetric leakage-compensated bit line WO2004025661A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003273284A AU2003273284A1 (en) 2002-09-10 2003-09-05 Static random access memory with symmetric leakage-compensated bit line

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/241,791 2002-09-10
US10/241,791 US6707708B1 (en) 2002-09-10 2002-09-10 Static random access memory with symmetric leakage-compensated bit line

Publications (2)

Publication Number Publication Date
WO2004025661A2 WO2004025661A2 (en) 2004-03-25
WO2004025661A3 true WO2004025661A3 (en) 2004-12-09

Family

ID=31946378

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/027789 WO2004025661A2 (en) 2002-09-10 2003-09-05 Static random access memory with symmetric leakage-compensated bit line

Country Status (4)

Country Link
US (1) US6707708B1 (en)
AU (1) AU2003273284A1 (en)
TW (1) TWI232579B (en)
WO (1) WO2004025661A2 (en)

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Publication number Priority date Publication date Assignee Title
US6801463B2 (en) * 2002-10-17 2004-10-05 Intel Corporation Method and apparatus for leakage compensation with full Vcc pre-charge
US7092279B1 (en) * 2003-03-24 2006-08-15 Sheppard Douglas P Shared bit line memory device and method
US6967875B2 (en) * 2003-04-21 2005-11-22 United Microelectronics Corp. Static random access memory system with compensating-circuit for bitline leakage
US7123500B2 (en) * 2003-12-30 2006-10-17 Intel Corporation 1P1N 2T gain cell
US7224205B2 (en) * 2004-07-07 2007-05-29 Semi Solutions, Llc Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
US8247840B2 (en) * 2004-07-07 2012-08-21 Semi Solutions, Llc Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode
US7683433B2 (en) 2004-07-07 2010-03-23 Semi Solution, Llc Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
US7375402B2 (en) * 2004-07-07 2008-05-20 Semi Solutions, Llc Method and apparatus for increasing stability of MOS memory cells
FR2874117A1 (en) * 2004-08-04 2006-02-10 St Microelectronics Sa MEMORY POINT OF SRAM TYPE, MEMORY COMPRISING SUCH A MEMORY POINT, READING METHOD AND ASSOCIATED WRITING METHOD
US7651905B2 (en) * 2005-01-12 2010-01-26 Semi Solutions, Llc Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts
US7898297B2 (en) * 2005-01-04 2011-03-01 Semi Solution, Llc Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits
US7212040B2 (en) * 2005-05-16 2007-05-01 Intelliserv, Inc. Stabilization of state-holding circuits at high temperatures
US7863689B2 (en) * 2006-09-19 2011-01-04 Semi Solutions, Llc. Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor
US8006164B2 (en) 2006-09-29 2011-08-23 Intel Corporation Memory cell supply voltage control based on error detection
US7812631B2 (en) * 2006-12-12 2010-10-12 Intel Corporation Sleep transistor array apparatus and method with leakage control circuitry
US20080273366A1 (en) * 2007-05-03 2008-11-06 International Business Machines Corporation Design structure for improved sram device performance through double gate topology
US7408800B1 (en) * 2007-05-03 2008-08-05 International Business Machines Corporation Apparatus and method for improved SRAM device performance through double gate topology
JP2009064482A (en) * 2007-09-04 2009-03-26 Nec Electronics Corp Semiconductor memory device
US8139400B2 (en) * 2008-01-22 2012-03-20 International Business Machines Corporation Enhanced static random access memory stability using asymmetric access transistors and design structure for same
US8207784B2 (en) * 2008-02-12 2012-06-26 Semi Solutions, Llc Method and apparatus for MOSFET drain-source leakage reduction
TWI514379B (en) * 2014-07-14 2015-12-21 Winbond Electronics Corp Memory device for reducing leakage current
US10229738B2 (en) 2017-04-25 2019-03-12 International Business Machines Corporation SRAM bitline equalization using phase change material

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11260063A (en) * 1998-03-10 1999-09-24 Hitachi Ltd Semiconductor device
US6262911B1 (en) * 2000-06-22 2001-07-17 International Business Machines Corporation Method to statically balance SOI parasitic effects, and eight device SRAM cells using same
US20030179600A1 (en) * 2002-03-19 2003-09-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

Family Cites Families (2)

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Publication number Priority date Publication date Assignee Title
US4914629A (en) * 1988-09-07 1990-04-03 Texas Instruments, Incorporated Memory cell including single event upset rate reduction circuitry
US5426614A (en) * 1994-01-13 1995-06-20 Texas Instruments Incorporated Memory cell with programmable antifuse technology

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11260063A (en) * 1998-03-10 1999-09-24 Hitachi Ltd Semiconductor device
US6262911B1 (en) * 2000-06-22 2001-07-17 International Business Machines Corporation Method to statically balance SOI parasitic effects, and eight device SRAM cells using same
US20030179600A1 (en) * 2002-03-19 2003-09-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 14 22 December 1999 (1999-12-22) *

Also Published As

Publication number Publication date
TW200410398A (en) 2004-06-16
US6707708B1 (en) 2004-03-16
US20040047176A1 (en) 2004-03-11
WO2004025661A2 (en) 2004-03-25
TWI232579B (en) 2005-05-11
AU2003273284A1 (en) 2004-04-30

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