WO2001065565A1 - An improved high density memory cell - Google Patents

An improved high density memory cell Download PDF

Info

Publication number
WO2001065565A1
WO2001065565A1 PCT/CA2001/000273 CA0100273W WO0165565A1 WO 2001065565 A1 WO2001065565 A1 WO 2001065565A1 CA 0100273 W CA0100273 W CA 0100273W WO 0165565 A1 WO0165565 A1 WO 0165565A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
node
cell
line
memory cell
Prior art date
Application number
PCT/CA2001/000273
Other languages
French (fr)
Inventor
Richard C. Foss
Cormac O'connell
Original Assignee
Mosaid Technologies Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Incorporated filed Critical Mosaid Technologies Incorporated
Priority to GB0219973A priority Critical patent/GB2375642B/en
Priority to KR1020027011589A priority patent/KR100743808B1/en
Priority to CA002401025A priority patent/CA2401025A1/en
Priority to DE10195853T priority patent/DE10195853T1/en
Priority to JP2001564165A priority patent/JP4903338B2/en
Priority to AU2001242125A priority patent/AU2001242125A1/en
Publication of WO2001065565A1 publication Critical patent/WO2001065565A1/en
Priority to US10/227,380 priority patent/US6751111B2/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/12Static random access memory [SRAM] devices comprising a MOSFET load element
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/043Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using capacitive charge storage elements

Definitions

  • This invention relates to memory devices and more particularly, to a memory cell for embedded memory applications
  • One particular application discussed herein is constructing content addressable memories (CAM's) for use in embedded memory systems
  • SRAMs static random access memories
  • DRAMs dynamic random access memories
  • Embedded memory applications typically involve combining memory and other logic functions onto a single semiconductor device resulting in very high bandwidth operation between the memory portion and the other circuitry.
  • Common applications for embedded memory systems include microprocessor cache memorv . microcontroller memory, and various system-on-a-chip applications
  • memory plays an important role in increasing the performance of networking systems in general, and specifically for example in the area of Layer 3 Fast Ethernet and Gigabit switches
  • One particular role which memory plays in such switches is for fast address look-ups
  • this type of operation involves comparing an incoming data packet's address information with an existing database consisting of possible addresses indicating where the incoming packet can be forwarded
  • This type of operation is very well suited for implementation using Content Addressable Memory (CAM) especially as network protocols change and databases used for storing such information continue to grow
  • CAM Content Addressable Memory
  • CAMs have not gained as widespread usage as DRAMs or SRAMs due to the larger cell size required to implement CAM
  • ASICs application specific circuits
  • CAMs have been often used to implement application specific memories for such applications as table look-up and associative computing
  • CAM is best suited in applications that require the implementation of high performance wide word search algorithms In such cases.
  • CAM-based searches provide an advantage over other search algorithms implementations, such as software-implemented binary tree based searches for example This is due to CAM's capability of performing searches using very wide words and searching multiple locations in parallel
  • data in a CAM is accessed based on contents of its cells rather than on physical locations
  • a CAM operates by comparing information to be searched, referred to as search data, against the contents of the CAM When (and if) a match is found, the match address is returned as the output
  • CMOS six transistor (6T) SRAM Cell has been widely used for many years, as shown schematically in Figure 1 It is a simple robust arrangement and, depending on the ratio of the access transistors Ta and the inverter devices Tn and their complementary loads Tp, may be read either non-destructively or destructively, in which latter case, the data stored must be sensed and written back into the cell Even the destructive read is a far simpler operation than the corresponding operation of a classic IT cell DRAM
  • the drawback of this cell is that it requires a relatively large area for the six transistors and, now increasingly important in modern processes, their contacts and internal cross-coupled interconnections
  • the need for both complementary bit and bit lines to each cell is a further constraint on packing density as is the need to supply voltages Vdd and Vss to each cell
  • this new cell consists of fewer transistors than typical SRAM memory cells and does not require a cell capacitor to store charge. It is further desirable to use this type of high density memory cell to construct embedded cells for CAM ' s
  • the present invention seeks to provide a memory cell for high density cell applications having a smaller cell size than conventional SRAM cells, and that is capable of static data storage that is, no refresh of data in the cell is required
  • An advantage of the present invention is to replace both regular and embedded SRAM and DRAM cells.
  • the memory cell can be built using a regular logic process with requiring additional process steps associated with complex capacitive structures
  • the memory cell is particularly well suited to complex functions requiring independent read and ⁇ te paths and content-addressable memo ⁇ es (CAMs)
  • a memory cell comprising
  • an access transistor coupled between a bit line and the input node of said inverting stage for selectively coupling said bit line to said inverting stage input node in response to a control signal received along a control line
  • Figure 1 is a schematic diagram of an 6T SRAM cell, according to the prior art
  • Figure 2 is a schematic diagram of an 5T SRAM cell, according to the prior art
  • Figure 3 is a schematic diagram of an 4T SRAM cell with a resistive load, according to the prior art
  • Figure 4 is a schematic diagram of a "loadless" 4T SRAM cell, according to the prior art
  • Figure 5 is a memory cell, according to an embodiment of the present invention.
  • Figure 6 is a ternary CAM cell, according to a further embodiment of the invention.
  • Figure 7 is a schematic diagram of an n-channel quad configuration, according to an embodiment of the present invention
  • Figure 8 is a schematic diagram of a ternary CAM cell, according to a another embodiment of the present invention.
  • Figure 9 is a schematic diagram of an asymmetric 4T memory cell according to a further embodiment
  • Figure 10 is a schematic diagram of a memory cell according to another embodiment
  • Figure 1 1 is a schematic diagram of a binary CAM cell using the cell of Figure 10,
  • Figure 12 is a schematic diagram of a full ternary cam cell using the cells of Figure 10,
  • Figure 13 is a schematic diagram of a simplified ternary cell of Figure 12.
  • Figure 14 is a schematic diagram of a layout of ' ⁇ the ternary CAM cell of figure 12
  • the SRAM cell 100 comprises a pair of cross-coupled NMOS devices 102 and 104 for drive transistors and a pair of PMOS devices 106 and 108 coupled to respective nodes C and D for access transistors
  • This configuration resembles a loadless CMOS four-transistor (4T) DRAM cell used in the 1970's except that in this prior art implementation, the cross-coupled devices are NMOS and the access devices are PMOS
  • the access transistors 106 and 108 are connected to respective bit lines ( BL I BL ), with their gates connected to a word line (WL)
  • the circuit arrangement 100 is constructed with the transistors having characteristic such that if the bit lines ( BL I BL ) are precharged logic high (VDD) and the manufactu ⁇ ng process and/or the p-channel gate voltage is manipulated to ensure that the PMOS devices have higher leakage current than the NMOS devices, the cell 100 will operate similar to a standard
  • bit lines ( BL I BL ) are precharged to VDD supply (high) and the word line WL is also precharged to VDD
  • the cell maintains this stored data, l e.
  • the cell 200 is comprised of a pair of crossed-coupled PMOS transistors 202 and 204 each having their respective sources coupled to a VDD supply and transistor 204 having its dra coupled at node A to an NMOS pull-down transistor 208, thereby forming an inverting stage, and transistor 202 having its source coupled at node B to an NMOS access transistor 206 which couples node B to a bit line BL w hile its gate is coupled to a word line WL.
  • the NMOS transistor 208 has its source coupled to the word line WL while its gate is coupled to node A of the cross-coupled pair.
  • the cell 200 provides at least one "hard" node A (i.e. a node which maintains the voltage level without significant degradation as long as the WL remains enabled thereby providing a ground for a possible search interrogation in a CAM operation.
  • a "keeper" current is supplied by a resistive load or other similar means, the cell 200 may be operated in either dynamic or static mode.
  • the cell 200 is shown "upside down” compared to the cell 100 of Figure 4, that the transistor types of the cross-coupled and access devices are reversed
  • the cell 200 can equally well be implemented with N-channel devices as the cross-coupled transistors 202 and 204 and P-channel transistors as access dev ices 206 and 208 while the bit line is held normally high
  • the cell configuration 200 has its word line (WL) no ⁇ nally held at logic low or ground voltage and is only pulsed high briefly to turn on the access device 206 after which it is returned to the ground voltage level Therefore, the word line (WL) serves as the ground for the inverting stage of the circuit
  • WL word line
  • the bit line BL is set high or low depending on the logic of the data to be w ⁇ tten
  • the word line WL is then pulsed for a predetermined pe ⁇ od During the time period when the WL is high, data is passed to the "soft" node B (1 e a node which will experience signal degradation without unless refreshing to the node is provided) via the access device 206 Once WL returns to logic low , data is stored on the "soft" node B and the in erted or "hard” node A
  • the bit line BL begins precharged low and the word line WL level rises A pulse of current begins to flow into the bit line as the high stored on node B is read onto the bit line with a threshold v oltage drop across access transistor 206 so that the voltage on the bit line eventually reaches VDD- V ⁇ N
  • This voltage difference on the bit line can be detected using well known DRAM type sensing, by comparing another half bit-line to which is attached a dummy cell having half the size of a normal cell Since the data sensed on the bit line BL has to be restored onto node B (the "soft node") in order for the cell to retain the correct data, once the data is sensed and amplified on the bit line this logic high value is written back into node B while the word line remains high The write back is then completed as the word line falls
  • the bit line begins precharged and the w ord line rises Since there is no voltage difference between the bit line w hich is precharged low and the value stored on node B, no current flows and the value on node B remains unchanged
  • the value on node B is maintained as described earlier bv ensuring that the leakage current through the NMOS access device 206 is greater than the leakage current through the PMOS feedback transistor 202, I e IOFF-N » IOFF-P
  • This can be accomplished as described earlier by applying a voltage lo er than VSS to the p-well of the NMOS device 206 (for example, an on-chip generated negative voltage supply VBB) This will effectively low er the threshold voltage of NMOS device 206 relative to the threshold voltage of PMOS device 202 and ensure that a larger leakage current flows through NMOS device 206 than through PMOS device 202, thereby maintaining the logic low value on node
  • this sense-restore function is only needed during a read operation in a CAM if (a) the cell is operating as a dynamic CAM (DCAM) cell or (b) as a dynamic back-up mode to static mode operation or (c) there is a need to read the cell contents (such as in testing or content read-out operating mode) In general however, for common search and compare operations generally performed by CAMs, the read operation is not needed
  • the cell configuration of the present invention may be utilized to implement a ternary CAM cell
  • Any ternary CAM cell should be capable of both storing a "don't care" state and searching with a masked bit Accordingly, the CAM cell must have three states for each, which in practice requires a double binary cell, l e the cell must be able to store a logic "0" a logic "1 " and a logic "don't care” and must also be able to mask these three values
  • a 10T ternary CAM cell 300 is shown constructed according to an embodiment of the invention, which comprises a pair of cells memory cells 200 as described ith reference to Figure 5 and additional devices 306 and 308 for implementing an exclusive OR (XOR) function 304 required for search and compare operations
  • XOR exclusive OR
  • PMOS transistors 306 and 308 have their respectiv e source-drain circuits connected between respective "hard” nodes A and A' and a match line MA TCH Their respectiv e gates are connected to complementary search lines SEARCH and SEARCLI applied to the gates of transistors 306 and 308 respectivel
  • the AND gating operates so that SEARCLI and SEARCH compare with the stored data
  • the MATCH line w ill only stay low if "hard" node A and SEARCH are both low (and “hard” node A' and SEARCH are high) or if both A and A' are both low or SEARCH and SEARCH are high (or of course, A and A ' are low and
  • the search / match transistors 306,308 may be implemented as ⁇ channel devices without risk of disturbing the "soft" nodes B and B'
  • the search line now puts current into the word line w hich is low thus the match detect circuit must respond to current dra n from the voltage of the match line which is between VDD and VDD-V I K , where V ! ⁇ is source-following enhanced
  • V ! ⁇ is source-following enhanced
  • a difficulty with this implementation is that the basic cell may need to have a voltage V ⁇ > greater than V
  • an N-channel 4-trans ⁇ stor circuit configuration 400 is shown The two extra devices are connected as common-gate, common-source to the "hard" node pull- down transistor 404 and shared source-drain to the search devices 406, 408.
  • This configuration still allow s some leakage current to flow into the low ord lines but places no sensing restrictions on the match line
  • Replacing all four transistors with p- channels may be the best solution in this polarity
  • these transistors may be common-gate, common-source with the transistors whose gates are connected to nodes A, A' and B,B' respectively This would make writing and searching operations nearly independent
  • a binary CAM needs only the one 4T-cell stored with a p-channel XOR quad driven by both nodes Such a cell thus has 8 transistors and 6 lines and is still capable of doing a masked search though not a stored "don't care" Clearly, there are a number of factors to weigh m choosmg the best compromise between circuit simplicity, area, and rugged operation
  • a complete versron of a ternary CAM implementation 500 is shown
  • the circuit 500 is based on p-channel access transistors Tl and Tl ', so the presumption is that P- channel leakage is greater than N, or that the cell operates dynamically
  • the word line WL is normally logic high and the match line is pulled down by all cells where a mismatch occurs.
  • a logic low stored on the "hard” nodes A and A' prevents a pull down as does logic low levels stored on the SEARCH and SEARCH lines As there are actually four states, other functions are also possible A logic high on both the "hard” nodes A and A' w ill inhibit any match bem detected regardless of search word unless that search word is masked by logic low on both SEARCH and SEARCH lines
  • the basic cell confguratron 200 of Frgure 5 could be used for embedded SRAM applications such as cache memory in microprocessors/microcontrollers
  • the cell can be a "write-only" cell with search logic connected to it Alternativ ely, it can be read destructiv ely, its state sensed and restored back in, whrch is how it would be operated dynamically
  • FIG. 9 A further embodrment of the invention a basic asymmetric 4T cell 900 is shown in Figure 9 It combines a regular CMOS inv erter formed bv a pair of transistors 906 SL 905 w ith a single p-channel access transistor and an n-pull-down to a 'soft" node 904 Like the regular 4T cells, this "soft" node will require one of the means noted for regular 4T cells to sustam a logic "one" level This implies regular refreshing by pulsing low the word line or means to control p-channel leakage to be greater than that pulling do n on that node while it stores a logic one
  • the word line logic high level can be regulated to a lev el lower than Vdd or a low threshold PMOS device can be used as the access transistor for mstance
  • Figure 10 eliminates the need for a Vdd supply by connecting the inverter power supply node to the word line which is maintained normally at logic high except for a small pulse to enable the access transistor 1002 As well as eliminating a metal line running through the memory cell, this approach eases writing of date, as it is not then necessary for the p-channcl access transistor 1002 to overcome the n-channel's 1004 role of holding down the "soft" node w hile it stores a logic zero, as the drive to the n-channel is automatically removed The cost is a more difficult read
  • the cell now only extracts a limited amount of charge before the n-channel turns off The cell thus behaves very much like a I T cell DRAM working with a bit line pre-charged to logic high with an effecti e capacitance w hich may be some 10's of fF As such, it would need
  • FIG. 1 1 there is show n a Binary CAM cell 1 100 wherein both nodes B and A of the memory cell are connected as inputs to the exclusiv e-NOR gate The output of the gate goes as a w ired-OR to the match line which w ill have a path to ground if there is any mismatch between stored data and that on the search and search lines A double logic zero will result in the cell data being ignored but there is no way to store a "Don't Care" state in the memory cell To store three states requires tw o bits of storage as is shown in the circuit 1200 of Figurel 2
  • FIG 14 there is shown generally at numeral 1400 a layout in a typical 0 18 micron logic process for the circuit for a ternary CAM cell as show n m Figure 12
  • FIG 14 there is shown a general layout of a ternary CAM cell, the circuit of which is show n Figure 12. Please note that they layout shown is for one half of the circuit as shown in Figure 1 .
  • the layout in Figure 14 is labelled on the diagram
  • the dashed lines enclose regions representing metal layers
  • the hatched lines represent regions corresponding to acti e regions
  • the continuous lines enclose regions of polysihcon.
  • the soft node partially or substantially surrounds the hard node and therefore ensurrng a tightly packed layout configuration
  • the hard and soft nodes consist of multiple contacts each composed of at least one metal layer

Abstract

A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for selectively coupling the data line and the inverting stage input, a feedback transistor coupled to the inverting stage input and being responsive to an output of the inverting stage for latching the inerting stage in a first logic state and whereby the cell is maintained in a second logic state by a leakage current flowing through the access transistor which is greater than a current flowing through the feedback transistor.

Description

AN IMPROVED HIGH DENSITY MEMORY CELL
This invention relates to memory devices and more particularly, to a memory cell for embedded memory applications One particular application discussed herein is constructing content addressable memories (CAM's) for use in embedded memory systems
BACKGROUND OF THE INVENTION
Semiconductor memory has continued to increase in density as a result of a number of technological advances in reducing transistor minimum feature sizes and increased flexibility in semiconductor device manufacturing capabilities Both static random access memories (SRAMs) as well as dynamic random access memories (DRAMs) have benefited from advances in commodity as well as embedded implementations Embedded memory applications typically involve combining memory and other logic functions onto a single semiconductor device resulting in very high bandwidth operation between the memory portion and the other circuitry. Common applications for embedded memory systems include microprocessor cache memorv . microcontroller memory, and various system-on-a-chip applications
In the networking industry, memory plays an important role in increasing the performance of networking systems in general, and specifically for example in the area of Layer 3 Fast Ethernet and Gigabit switches One particular role which memory plays in such switches is for fast address look-ups Typically, this type of operation involves comparing an incoming data packet's address information with an existing database consisting of possible addresses indicating where the incoming packet can be forwarded This type of operation is very well suited for implementation using Content Addressable Memory (CAM) especially as network protocols change and databases used for storing such information continue to grow
Historically CAMs have not gained as widespread usage as DRAMs or SRAMs due to the larger cell size required to implement CAM In application specific circuits (ASICs) however, CAMs have been often used to implement application specific memories for such applications as table look-up and associative computing For networking applications, CAM is best suited in applications that require the implementation of high performance wide word search algorithms In such cases. CAM-based searches provide an advantage over other search algorithms implementations, such as software-implemented binary tree based searches for example This is due to CAM's capability of performing searches using very wide words and searching multiple locations in parallel Typically, data in a CAM is accessed based on contents of its cells rather than on physical locations A CAM operates by comparing information to be searched, referred to as search data, against the contents of the CAM When (and if) a match is found, the match address is returned as the output
A general background discussion about the various types of CAM cells and their operation is gi en in the article, "Content-addressable memory core cells - A survey." by Kenneth Schultz in INTEGRATION, the VLSI journal 23 ( 1997) pg 171 - 188 As discussed in the article, CAM cells can be implemented with both SRAM and DRAM type memory cells There are clearly advantages and disadvantages to using both types of memories to build CAMs Generally, DRAM based CAMs have a higher density capacity due to the reduced number of elements required to build a cell as compared with SRAM based CAMs but suffer from the additional complication of requiring periodic refresh in order to maintain the stored data Various DRAM based CAM cells have been proposed such as US Patent No. 3,701 ,980 to Mundy, and US Patent No's 4,831.585, 4.799, 192 to Wade and Sodini and more recently to Lines ct al in US application 09'533,128 assigned to MOSAID Technologies
For example, a CMOS six transistor (6T) SRAM Cell has been widely used for many years, as shown schematically in Figure 1 It is a simple robust arrangement and, depending on the ratio of the access transistors Ta and the inverter devices Tn and their complementary loads Tp, may be read either non-destructively or destructively, in which latter case, the data stored must be sensed and written back into the cell Even the destructive read is a far simpler operation than the corresponding operation of a classic IT cell DRAM The drawback of this cell is that it requires a relatively large area for the six transistors and, now increasingly important in modern processes, their contacts and internal cross-coupled interconnections The need for both complementary bit and bit lines to each cell is a further constraint on packing density as is the need to supply voltages Vdd and Vss to each cell
Also known for many years is the asymmetric 5T cell, as shown schematically in Figure 2 This is a small improv ement over the 6T cell of Figure 1 but the added difficulty in ensuring reliable w riting and the slower sensing on the single unbalanced bit line means that it is much less used
Finally there are a number of versions of 4T cells A common arrangement uses very high value resistors replacing the cross-coupled PMOS loads, as shown schematically in Figure 3 These simply have to overcome the leakage of the cell storage nodes The logic high level is also restored from the bit line each time the cell is accessed and the cell can thus operate in a dynamic mode
Several attempts have also been made to make the access transistors serve much the same function as the resistive loads, feeding charge from the bit lines to maintain a "one" level In the mid 1970's, Intel described a "Planar Refresh" I DRAM using cells with four transistors with the word lines periodically pulsed to refresh all cells simultaneously More recently, a four-transistor (4T) approach was presented by NEC, "A 16Mb 400MHz Loadless CMOS Four-Transistor SRAM Macro," ISSCC, February, 2001 w hich used p-channel access transistors with higher leakage than the n-channel cross-coupled devices The above circuits have some disadvantages in that for many memory applications, there is an increased demand for single chip solutions or so called syste - on-a-chip solutions, which require the merging of memory and logic functions onto a single semiconductor chip For DRAM cells, the DRAM fabrication typically requires special processing steps to construct the cell capacitor structures, such as stacked or trench cell capacitors Conversely, SRAM memory cells can be easily implemented by using standard logic processes or so-called "non-DRAM processes" A disadvantage however of SRAM memory, is that an SRAM cell typically comprised of 6T or 4T plus 2 resistors, takes up substantially more silicon area than a single transistor plus capacitor found in a typical DRAM cell When used to construct ternary CAM (three logic state) memory cells, these characteristics of DRAM and SRAM cells are amplified due to the additional complexity required to implement the exclusive NOR function required of a typical ternary CAM cell resulting in relati ely large CAM memory cells And although DRAM based CAMs provide a densitv advantage over SRAM based CAMs, the special fabrication process steps typically required for DRAM based technology limit the current potential of DRAM based CAMs in embedded memory applications
While processes offering DRAM process steps combined w ith regular logic capability are becoming more available, there is increasing concern that the complexity and cost justify their use only in a limited number of applications More importantly, the time delay between the availability in the industry of such processes relative to simpler all-logic processes for a given geometry, further impacts the economic case for embedding DRAM Thus for a given memory-to-logic ratio on a die, the die will actuallv be larger in the case of using a merged DRAM/logic 0 25 micron process to implement the memory portion vs using SRAM on an all-logic 0 18 micron process to implement the memory portion. This is particularly problematic in applications such as CAM with a high logic overhead even in stand-alone form which incur an even greater area penalty when embedded
As further considerations, portability between different foundry processes is poorer for the merged process and there are CAD tool inadequacies at this time.
Accordingly, primarily although not exclusively for embedded memory applications, it is desirable to provide a memory cell which benefits from DRAM based high density characteristics but can be implemented in a pure logic process, requiring no additional fabrication process steps for constructing capacitive structures Preferably, this new cell consists of fewer transistors than typical SRAM memory cells and does not require a cell capacitor to store charge. It is further desirable to use this type of high density memory cell to construct embedded cells for CAM's
SUMMARY OF THE INVENTION
The present invention seeks to provide a memory cell for high density cell applications having a smaller cell size than conventional SRAM cells, and that is capable of static data storage that is, no refresh of data in the cell is required An advantage of the present invention is to replace both regular and embedded SRAM and DRAM cells. In particular, the memory cell can be built using a regular logic process with requiring additional process steps associated with complex capacitive structures In addition, the memory cell is particularly well suited to complex functions requiring independent read and πte paths and content-addressable memoπes (CAMs)
In accordance with this invention, there is provided a memory cell comprising
(a) an CMOS inverting stage having an input node and an output node,
(b) an access transistor coupled between a bit line and the input node of said inverting stage for selectively coupling said bit line to said inverting stage input node in response to a control signal received along a control line, and
(c) a feedback element coupled between said inverting stage output node and a supply line for latching said inverting stage in a first logic state in response a signal at the input node of said inverting stage.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features of the preferred embodiments of the invention will become more apparent in the following detailed description in which reference is made to the appended drawings wherein Figure 1 is a schematic diagram of an 6T SRAM cell, according to the prior art;
Figure 2 is a schematic diagram of an 5T SRAM cell, according to the prior art, Figure 3 is a schematic diagram of an 4T SRAM cell with a resistive load, according to the prior art,
Figure 4 is a schematic diagram of a "loadless" 4T SRAM cell, according to the prior art;
Figure 5 is a memory cell, according to an embodiment of the present invention;
Figure 6 is a ternary CAM cell, according to a further embodiment of the invention; Figure 7 is a schematic diagram of an n-channel quad configuration, according to an embodiment of the present invention, Figure 8 is a schematic diagram of a ternary CAM cell, according to a another embodiment of the present invention,
Figure 9 is a schematic diagram of an asymmetric 4T memory cell according to a further embodiment, Figure 10 is a schematic diagram of a memory cell according to another embodiment,
Figure 1 1 is a schematic diagram of a binary CAM cell using the cell of Figure 10,
Figure 12 is a schematic diagram of a full ternary cam cell using the cells of Figure 10,
Figure 13 is a schematic diagram of a simplified ternary cell of Figure 12, and
Figure 14 is a schematic diagram of a layout of 'Λ the ternary CAM cell of figure 12
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to Figure 4, there is shown a loadless CMOS 4T SRAM cell 100 according to the prior art The SRAM cell 100 comprises a pair of cross-coupled NMOS devices 102 and 104 for drive transistors and a pair of PMOS devices 106 and 108 coupled to respective nodes C and D for access transistors This configuration resembles a loadless CMOS four-transistor (4T) DRAM cell used in the 1970's except that in this prior art implementation, the cross-coupled devices are NMOS and the access devices are PMOS The access transistors 106 and 108 are connected to respective bit lines ( BL I BL ), with their gates connected to a word line (WL) The circuit arrangement 100 is constructed with the transistors having characteristic such that if the bit lines ( BL I BL ) are precharged logic high (VDD) and the manufactuπng process and/or the p-channel gate voltage is manipulated to ensure that the PMOS devices have higher leakage current than the NMOS devices, the cell 100 will operate similar to a standard resistance loaded SRAM cell In other words, in order to retain the data without a refresh cycle, an OFF-state current of the PMOS device lorr p has to be higher than that of the NMOS device IQΓΓ N The cell 100 uses the PMOS access transistors 106 and 108 as load devices to maintain the data in the cell without the need for a refresh operation. More specifically, in a stand-by case, the bit lines ( BL I BL ) are precharged to VDD supply (high) and the word line WL is also precharged to VDD Assuming that data in the cell is stored as a logic high ('H' ) or VDD level at node C and logic low ('L') or VSS level at node D, (the opposite state, i.e 'H' on node D and 'L' on node C could also be stored, of course) the cell maintains this stored data, l e. the 'H' at node C by ensuring that the leakage or OFF-state current through the PMOS access transistor 108 is greater than the OFF-state current through the NMOS transistor 104, i.e I0ι i p »Ioι i \ This is achieved by increasing the threshold voltage of the NMOS device relative to the threshold v oltage of the PMOS device so as to allow more leakage current to flow through the PMOS device 1 8 than through the NMOS device 104 As a result, the OFF-state current of the NMOS transistor 104 with VDS=1 8V (I e the voltage across its drain-source) is lower than the OFF-state current of the PMOS transistor 108 with VDS=0 05 V by approximately two orders of magnitude
There are a number of ways for biasing the "leakage current race" in the circuit of Figure 4. Simply controlling transistor threshold voltages V-i 's by selective gate ion implantation is one. P-channel devices built with N-type polysihcon gates tend to leak due to adverse work function effects creating a buried channel If the issue is predominantly one of sub-threshold leakage, then adjusting w idth and/or lengths mav accomplish the desired relative difference in threshold voltages Another solution is to apply a bias voltage to the transistor's tub or substrate (depending on device polarity) to adjust the threshold voltage For example, for a circuit having PMOS cross-couples and NMOS access devices and aiming to have NMOS leakage current greater than the PMOS leakage current, by applying a voltage to (or pumping) the n-type tub (1 e. the tub in w hich the PMOS devices reside) to a voltage higher than VDD, w ould increase the PMOS devices' threshold v oltage, V \ \>, thereby lowering the P-sub-threshold current This approach would only be effecti e if leakage from the source or drain of the PMOS transistor to the n-type tub did not excessively increase and thereby eliminate the gain in VTp Referring now to Figure 5 there is shown generally by numeral 200 an improved memory cell, according to an embodiment of the present invention. The cell 200 is comprised of a pair of crossed-coupled PMOS transistors 202 and 204 each having their respective sources coupled to a VDD supply and transistor 204 having its dra coupled at node A to an NMOS pull-down transistor 208, thereby forming an inverting stage, and transistor 202 having its source coupled at node B to an NMOS access transistor 206 which couples node B to a bit line BL w hile its gate is coupled to a word line WL. The NMOS transistor 208 has its source coupled to the word line WL while its gate is coupled to node A of the cross-coupled pair. Thus, it may be seen that the cell 200 of Figure 5 is an improvement over the cell 100 show n schematically in Figure 4. in that there is a reduction of one bit line and the ground line VSS. In addition, the cell 200 provides at least one "hard" node A (i.e. a node which maintains the voltage level without significant degradation as long as the WL remains enabled thereby providing a ground for a possible search interrogation in a CAM operation. Just as regular 4T SRAM cell can operate dynamically or statically, if a "keeper" current is supplied by a resistive load or other similar means, the cell 200 may be operated in either dynamic or static mode. Schematically, the cell 200 is shown "upside down" compared to the cell 100 of Figure 4, that the transistor types of the cross-coupled and access devices are reversed However, depending on how the leakages between P and N are controlled, the cell 200 can equally well be implemented with N-channel devices as the cross-coupled transistors 202 and 204 and P-channel transistors as access dev ices 206 and 208 while the bit line is held normally high This alternate embodiment w ill be discussed in further detail with reference to Figures 9 and 10 Referring back to Figure 5, the cell configuration 200 has its word line (WL) noπnally held at logic low or ground voltage and is only pulsed high briefly to turn on the access device 206 after which it is returned to the ground voltage level Therefore, the word line (WL) serves as the ground for the inverting stage of the circuit This has a drawback of increasing the word line capacitance, but has the advantage of eliminating a metal line running through the CAM cell and simplifying writing to the cell. The operation of the cell may be explained as follows in a wπte operation, the bit line BL is set high or low depending on the logic of the data to be wπtten The word line WL is then pulsed for a predetermined peπod During the time period when the WL is high, data is passed to the "soft" node B (1 e a node which will experience signal degradation without unless refreshing to the node is provided) via the access device 206 Once WL returns to logic low , data is stored on the "soft" node B and the in erted or "hard" node A
There are two write operation cases where a change of state of the cell 200 is possible The first is writing of a logic low into a cell w hich currently stores a logic high, and the second is the writing of a logic high into a cell which currently stores a logic low The other two possibilities are the riting of a logic low into a cell which already stores a logic low and a writing of a logic high into a cell which already stores a logic high These latter two possibilities are also supported but wrll not be described in detail since no change of state in the cell occurs Firstly, consider the case of writing a logic low into a cell, which stores a logic high Prior to the write operation beginning, the "soft node" B is logic high and the inverted or "hard node" A is logic low As previously mentioned, the write line WL is kept logic low during "standby" Next, a logic low is loaded onto the bit line BL and the WL begins to rise turnmg on the access device 206, thereby bringing node B to a logic low, which in turn, sets node A to logic high through the pull-up PMOS transistor 204 in the inverting stage The PMOS transistor 202, which is connected to the "soft" node B, is therefore turned off Once the WL is turned off, the access device 206 turns off so both the access device 206 and the pull-up PMOS transistor 202 are both off The logic low data on node B is kept in this state through leakage current only Specifically, the leakage or OFF-state current flowing through the NMOS access device 206 is greater than the OFF-state current flowing through the PMOS pull-up transistor 202 connected to node B This can be accomplished for example, by setting a threshold voltage of the NMOS transistor 206 to be lower than that of the PMOS transistor 202 This lets the access NMOS dev ice 206 conduct more than the PMOS device 202 Alternately, the threshold voltages of the NMOS and PMOS devices can be altered by applying a higher than VDD voltage to the N-type tub in which the PMOS device lies Secondly, consider the case of writing a logic high into a cell that stores a low In essence a similar process as described abov e is executed A logic high is placed on the bitlme BL The word line WL is brought to logic high turning ON the access NMOS device 206 This passes a VDD - V TN lev el to node B (the threshold voltage drop occurs across the NMOS access device 206) The NMOS control device 208 is now ready to tum ON The VDD level at the access transistor 206 occurs w hen the bit line BL is logic high When the WL is brought to logic low again, the NMOS device 208 turns fully ON and pulls node A to a low logic level This turns on PMOS device 202 fully thus latching node B high In this state, no leakage current is needed to keep the data stored on nodes B and A since the logic low on node A. ensures that node B is maintained high
The following describes the reading operation For the case ot reading a logic high stored on node B (and a logic low on node A), the bit line BL begins precharged low and the word line WL level rises A pulse of current begins to flow into the bit line as the high stored on node B is read onto the bit line with a threshold v oltage drop across access transistor 206 so that the voltage on the bit line eventually reaches VDD- VιN This voltage difference on the bit line can be detected using well known DRAM type sensing, by comparing another half bit-line to which is attached a dummy cell having half the size of a normal cell Since the data sensed on the bit line BL has to be restored onto node B (the "soft node") in order for the cell to retain the correct data, once the data is sensed and amplified on the bit line this logic high value is written back into node B while the word line remains high The write back is then completed as the word line falls
For the case of reading a logic low stored on node B (and a logic high on node A), the bit line begins precharged and the w ord line rises Since there is no voltage difference between the bit line w hich is precharged low and the value stored on node B, no current flows and the value on node B remains unchanged Once the word line falls, the value on node B is maintained as described earlier bv ensuring that the leakage current through the NMOS access device 206 is greater than the leakage current through the PMOS feedback transistor 202, I e IOFF-N » IOFF-P This can be accomplished as described earlier by applying a voltage lo er than VSS to the p-well of the NMOS device 206 (for example, an on-chip generated negative voltage supply VBB) This will effectively low er the threshold voltage of NMOS device 206 relative to the threshold voltage of PMOS device 202 and ensure that a larger leakage current flows through NMOS device 206 than through PMOS device 202, thereby maintaining the logic low value on node B
It must be remembered that this sense-restore function is only needed during a read operation in a CAM if (a) the cell is operating as a dynamic CAM (DCAM) cell or (b) as a dynamic back-up mode to static mode operation or (c) there is a need to read the cell contents (such as in testing or content read-out operating mode) In general however, for common search and compare operations generally performed by CAMs, the read operation is not needed
In constructing cell 200 of the present invention, use is made of both P and N devices thus a trench isolated process w ith tight P+ to N+ spacing would be preferable In a further embodiment of the present invention, the cell configuration of the present invention may be utilized to implement a ternary CAM cell Any ternary CAM cell should be capable of both storing a "don't care" state and searching with a masked bit Accordingly, the CAM cell must have three states for each, which in practice requires a double binary cell, l e the cell must be able to store a logic "0" a logic "1 " and a logic "don't care" and must also be able to mask these three values Referring to Figure 6, a 10T ternary CAM cell 300 is shown constructed according to an embodiment of the invention, which comprises a pair of cells memory cells 200 as described ith reference to Figure 5 and additional devices 306 and 308 for implementing an exclusive OR (XOR) function 304 required for search and compare operations There are numerous ways of implementing the XOR function given NMOS and/or PMOS devices each implementation having circuit and layout advantages and disadv antages In Figure 6, AND gating bet een the source and the gate of P channel devices 306, 308 is shown. Specifically, PMOS transistors 306 and 308 have their respectiv e source-drain circuits connected between respective "hard" nodes A and A' and a match line MA TCH Their respectiv e gates are connected to complementary search lines SEARCH and SEARCLI applied to the gates of transistors 306 and 308 respectivel The AND gating operates so that SEARCLI and SEARCH compare with the stored data The MATCH line w ill only stay low if "hard" node A and SEARCH are both low (and "hard" node A' and SEARCH are high) or if both A and A' are both low or SEARCH and SEARCH are high (or of course, A and A' are low and
SEARCH and SEARCH are high) All other combinations result in MA TCH being pulled up but only as far as VDD -V n>, where V rp is increased by the source-tub bias as it is source-following This requires a match sensing circuit which will detect the difference between current flowing or not flowing into a level between VSS and VSS +
NI P
The search / match transistors 306,308 may be implemented as Ν channel devices without risk of disturbing the "soft" nodes B and B' However, the search line now puts current into the word line w hich is low thus the match detect circuit must respond to current dra n from the voltage of the match line which is between VDD and VDD-V I K, where V ! Ν is source-following enhanced A difficulty with this implementation is that the basic cell may need to have a voltage V π> greater than V | Alternatively, a more conventional 4-transιstor XOR crrcuit may be implemented This circuit however requires two additional transistors compared to the circuit 300 but in general, these transistors require very little additional area. Referring to Figure 7, an N-channel 4-transιstor circuit configuration 400 is shown The two extra devices are connected as common-gate, common-source to the "hard" node pull- down transistor 404 and shared source-drain to the search devices 406, 408. This configuration still allow s some leakage current to flow into the low ord lines but places no sensing restrictions on the match line Replacing all four transistors with p- channels may be the best solution in this polarity To avoid any coupling to the soft node B, these transistors may be common-gate, common-source with the transistors whose gates are connected to nodes A, A' and B,B' respectively This would make writing and searching operations nearly independent
It should be noted that a binary CAM needs only the one 4T-cell stored with a p-channel XOR quad driven by both nodes Such a cell thus has 8 transistors and 6 lines and is still capable of doing a masked search though not a stored "don't care" Clearly, there are a number of factors to weigh m choosmg the best compromise between circuit simplicity, area, and rugged operation
Referπng to Figure 8 a complete versron of a ternary CAM implementation 500 according to a preferred embodrment of the present mvention is shown The circuit 500 is based on p-channel access transistors Tl and Tl ', so the presumption is that P- channel leakage is greater than N, or that the cell operates dynamically The word line WL is normally logic high and the match line is pulled down by all cells where a mismatch occurs. A logic low stored on the "hard" nodes A and A' prevents a pull down as does logic low levels stored on the SEARCH and SEARCH lines As there are actually four states, other functions are also possible A logic high on both the "hard" nodes A and A' w ill inhibit any match bem detected regardless of search word unless that search word is masked by logic low on both SEARCH and SEARCH lines
The layout would likely cluster Tl , Tl ' and T2, T2' in a tub containing the corresponding devices of the inverted cell above Tl and Tl ' might share a gate contact T3, T4 and T5 will obviously cluster with the match line likely below VSS VSS may be a common connection to the inverted row of cells below
As an additional enhancement to the embodiment of Figure 8, a way of ensuring that data is maintained despite a read operation involves using a simple form of refresh similar to the planar refresh operation used in the aforementioned Intel I K DRAM If a selected cell's word line (which is normally held at VDD in this PMOS access implementation) is periodically dropped to VDD-V π» while its associated bit line is at logic high, this will "top up" a logic high lev el in the cells storing logic high's on their "soft" nodes B through a current mirror plus sub-threshold action This "top up" current will be easily overcome by NMOS pull-down transistors when turned on This will most likely work best with the symmetric version of the 4T SRAM cell as shown in Figure 4 or with an asymmetric version where the P-channel in the half- flop (T2 or T2'), as in Figure 8, has its source at VDD rather than WL since lowering the WL will reduce the driv e to the N-channel holding down a logic "zero" on the "soft" node Thrs refresh would be as transparent as the static operation described by with reference to Figure 4 and multiple word lines could be ghtched in this way
u - The basic cell confguratron 200 of Frgure 5 could be used for embedded SRAM applications such as cache memory in microprocessors/microcontrollers
In a CAM context, if static, the cell can be a "write-only" cell with search logic connected to it Alternativ ely, it can be read destructiv ely, its state sensed and restored back in, whrch is how it would be operated dynamically
A further embodrment of the invention a basic asymmetric 4T cell 900 is shown in Figure 9 It combines a regular CMOS inv erter formed bv a pair of transistors 906 SL 905 w ith a single p-channel access transistor and an n-pull-down to a 'soft" node 904 Like the regular 4T cells, this "soft" node will require one of the means noted for regular 4T cells to sustam a logic "one" level This implies regular refreshing by pulsing low the word line or means to control p-channel leakage to be greater than that pulling do n on that node while it stores a logic one The word line logic high level can be regulated to a lev el lower than Vdd or a low threshold PMOS device can be used as the access transistor for mstance
In some applrcatrons, the further srmplification of the circuit in Figure 9 may be possible This is shown in Figure 10 at numeral 1000 The embodiment of Figure 10 eliminates the need for a Vdd supply by connecting the inverter power supply node to the word line which is maintained normally at logic high except for a small pulse to enable the access transistor 1002 As well as eliminating a metal line running through the memory cell, this approach eases writing of date, as it is not then necessary for the p-channcl access transistor 1002 to overcome the n-channel's 1004 role of holding down the "soft" node w hile it stores a logic zero, as the drive to the n-channel is automatically removed The cost is a more difficult read The cell now only extracts a limited amount of charge before the n-channel turns off The cell thus behaves very much like a I T cell DRAM working with a bit line pre-charged to logic high with an effecti e capacitance w hich may be some 10's of fF As such, it would need to be sensed and restored However, in applications such as the CAM use, there is not actually a need to read the cell ia the bit line Instead, the cell controls inputs to an exclusive-OR gate to compare cell contents to search data Similarly, a separate read BL with a read WL controlling access would give separate read and write ports to the cell The reduced signal line count is especially useful m such multi-porting applications
Referring to Figure 1 1 , there is show n a Binary CAM cell 1 100 wherein both nodes B and A of the memory cell are connected as inputs to the exclusiv e-NOR gate The output of the gate goes as a w ired-OR to the match line which w ill have a path to ground if there is any mismatch between stored data and that on the search and search lines A double logic zero will result in the cell data being ignored but there is no way to store a "Don't Care" state in the memory cell To store three states requires tw o bits of storage as is shown in the circuit 1200 of Figurel 2
Λ further simplification of this cell is possible eliminating tw o of the transistors in the
Figure imgf000017_0001
gate is show n in the circuit 1300 of Figure 13 The »atιnu function between the cell contents and the SEARCH and SEARCH line is now performed between the gate and source of the search transistors The drawback with this arrangement is the requirement it places on the match sensing circuit The high level of the match line can only fall to Vdd-Vt before the search transistors may conduct in the reverse direction i f the cell is indicating a match Thus some foπn of current sensing or other means to distinguish between levels of Vdd-Vt is needed
Referring to figure 14, there is shown generally at numeral 1400 a layout in a typical 0 18 micron logic process for the circuit for a ternary CAM cell as show n m Figure 12
Referring to Figure 14, there is shown a general layout of a ternary CAM cell, the circuit of which is show n Figure 12. Please note that they layout shown is for one half of the circuit as shown in Figure 1 . For convenience, the layout in Figure 14 is labelled on the diagram In the layout, the dashed lines enclose regions representing metal layers, the hatched lines represent regions corresponding to acti e regions and the continuous lines enclose regions of polysihcon. In partrcular, it has been noted that the soft node partially or substantially surrounds the hard node and therefore ensurrng a tightly packed layout configuration Furthermore, the hard and soft nodes consist of multiple contacts each composed of at least one metal layer
Although the invention has been described with reference to certain specific embodiments, v arious modifications thereof w ill be apparent to those skilled in the art without departing from the spirit and scope of the inv ention as outlined in the claims appended hereto

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:1 A memory cell comprising(a) an CMOS inverting stage having an input node and an output node,(b) an access transistor coupled between a bit line and the input node of said inverting stage for selectively coupling said bit line to said inverting stage input node in response to a control signal received along a control line, and(c) a feedback element coupled between said inverting stage output node and a supply line for latching said inverting stage in a first logic state in response a signal at the input node of said inverting stage, such that said cell is maintained in a second logic state by a leakage current flowing through said access transistor which is greater than a current flowing through said feedback transistor2 A memory as defined in claim 1 , said control line being a word line.3 A memory as defined in claim 1 , said data line being a bit line4 A memory device as defined in claim 4, said transistors being PMOS devices and said access transistor being an NMOS device5 A memory cell comprising(a) an CMOS inverter comprised of first and second transistors,(b) a third transistor cross coupled gate-to-drain and drain-to-gate to said first transistor, and(c) a forth transistor of opposite polarity type to said third transistor coupling the drain of said third transistor to a bit line and being responsive to a word line control signal coupled to its gate A memory cell according to clarm 5 in w hich the transistor coupling the cell to the bit line is arranged to have a greater dram to source leakage current in its off condition than exists at the cell ode to w hich it is connected, thereby ensuring the retention of the logic level on that node when the cell is not actively pulling that node to the opposite stateA memory cell comprising an CMOS inverter, supplied from a fixed power rail and a word line, said word line replacing a second power rail, a third transistor cross coupled gate-to-drain and drain-to-gate with the transistor connected to the foxed supply and hav ing the same polarity type as said transistor, a fourth tiansistor of opposite polarity type to said third transistor coupling the drain of this third transistor to a bit line under the control of said word line coupling to its gateA memory cell according to claim 7 in w hich the transistor coupling the cell to the bit line is arranged to have a great drain to source leakage current in its off condition than exists at the cell node to w hich it is connected, thereby ensuring the retention of the level on that node when the cell is not actively pulling that node to the opposite gateA memoi y cell according to claim 5 to w hich is added one or more additional transistoi s coupling a node of the cell to an additional bit line or bit lines under the control of a word line or work lines thereby achieving a multiport type of memory cellA memoi y cell according to claim 7 to w hich is added one or more additional transistors coupling a node of the cell to an additional bit line or bit lines under the control of a word line or word lines thereby achieving a multiport type memory cell
1. A memory cell according to claim 5 to which is added four transistors, two connected to the memory cell nodes and in series with these two. tw o whose gates are driven by search and search bar lines parallel to the bit line, formrng an exclusive-NOR gate whose outpput drives a matchbar line parallel to the work dme, to form a binary CAM cell.
A memory cell according to claim 7 to w hich is added four transistors tow w ith their gates connected to the memory cell nodes and in series with those two, two whose gates are driven by search and searchbar lines parallel to the it line, forming an exclusiv e-NOR gate whose outpurt drives a matchbar line parallel tot he work line, to form a binary CAM cell
A memory cell according to claim 5 including a second memory cell according to claim 1 sharing a common word line, each of this pair of cells ha ing an equiv alent node connected to the gate of a transistor, said transistor in series w ith a transistor whose gate is driven by search and searchbar lines respectively, forming an exclusive-NOR gate whose output derives a matchbar line parallel to the word line, to form a ternary CAM cell.
A memory cell according to claim 7 including a second memory cell sharing a common word like, each of this pair of cells hav ing an equivalent node connected to the gate of a transistor, said transistor in series ith a transistor w hose gate is driven by search and scarhcbar lines respectively, forming an exclusive-NOR gate whose output drives a matchbar line parallel to the wordhne, to form a ternary CAM cell
A memory cell according to claim 7 in w hich the word line level in its inactiv e state is controlled to ensure the access transistor provides sufficient charge to the cell node to w hich it is coupled to on order to maintain the logic level w hen said node is not actively pulled to the supply line A memory cell according to clarm 7 in which the word lrne level in its activ e state is ontrolled such that when w riting in the state where the node to which the access transistor is connected is activ ely pulled to the supply line, the wπtten-in lev el is closer to said supply line
A memory cell according to claim 7 in which the access transistor is fabricate so as to have a lower threshold voltage than the load dev ice of the inverter
A memory cell according to claim 7 including a second memory cell, and sharing a common word line, each of this pair of cells having an additional transistor w ith its source connected to the inverter node, their gates connected to search and searchbar lines respectively and drains connected to a matchbar line parallel to the word line, to form a ternary CAM cell
A memory cell according to claim 19, mlcuding means for sensing the difference between match and mismatch states and differing by approximately a Vt on the matchbar line in the ternary CAM cell
A memory cell requiring only a bit line, a work line and a Vss supply capable of operating in a dynamic mode or retaining data in a static mode w hich can be fabricated using onl\ a regular CMOS logic process, thereby achiev ing superior functionality at low er process cost as compared to DRAM and high density as compared to conv entional SRAM
A layout for a memory cell comprising (a) a first region defining a hard node,
(a) a second region substantially surrounding said first node and defining a soft node each consisting of multiple contacts composed of at least one metal layer. and wherein the cell compπses an CMOS inverter comprised of first and second transistors; (b) a third transistor cross coupled gate-to-drain and drain-to-gate to said first transistor, and (b) a forth transrstor of opposite polarity type to said third transistor coupling at said soft node the drain of said third transistor to a bit line and being responsive to a word line control signal coupled to its gate
PCT/CA2001/000273 2000-03-03 2001-03-05 An improved high density memory cell WO2001065565A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
GB0219973A GB2375642B (en) 2000-03-03 2001-03-05 An improved high density memory cell
KR1020027011589A KR100743808B1 (en) 2000-03-03 2001-03-05 An improved high density memory cell
CA002401025A CA2401025A1 (en) 2000-03-03 2001-03-05 An improved high density memory cell
DE10195853T DE10195853T1 (en) 2000-03-03 2001-03-05 Improved high density memory cell
JP2001564165A JP4903338B2 (en) 2000-03-03 2001-03-05 Improved high density memory cell
AU2001242125A AU2001242125A1 (en) 2000-03-03 2001-03-05 An improved high density memory cell
US10/227,380 US6751111B2 (en) 2000-03-03 2002-08-26 High density memory cell

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002299991A CA2299991A1 (en) 2000-03-03 2000-03-03 A memory cell for embedded memories
CA2,299,991 2000-03-03

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/227,380 Continuation US6751111B2 (en) 2000-03-03 2002-08-26 High density memory cell

Publications (1)

Publication Number Publication Date
WO2001065565A1 true WO2001065565A1 (en) 2001-09-07

Family

ID=4165447

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2001/000273 WO2001065565A1 (en) 2000-03-03 2001-03-05 An improved high density memory cell

Country Status (9)

Country Link
US (1) US6751111B2 (en)
JP (1) JP4903338B2 (en)
KR (1) KR100743808B1 (en)
CN (1) CN1248237C (en)
AU (1) AU2001242125A1 (en)
CA (1) CA2299991A1 (en)
DE (1) DE10195853T1 (en)
GB (1) GB2375642B (en)
WO (1) WO2001065565A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007527591A (en) * 2003-06-30 2007-09-27 インテグレイテッド・デヴァイス・テクノロジー,インコーポレイテッド Memory with Ternary Search (TCAM) cell with small footprint and efficient layout aspect ratio

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2307240C (en) * 2000-05-01 2011-04-12 Mosaid Technologies Incorporated Matchline sense circuit and method
JP2002237190A (en) * 2001-02-07 2002-08-23 Kawasaki Microelectronics Kk Associative memory device and its constituting method
US20030123279A1 (en) * 2002-01-03 2003-07-03 International Business Machines Corporation Silicon-on-insulator SRAM cells with increased stability and yield
US6771525B2 (en) * 2002-05-31 2004-08-03 Mosaid Technologies Incorporated Method and apparatus for performing variable word width searches in a content addressable memory
US20060203529A1 (en) 2003-09-05 2006-09-14 William Radke Cutting CAM peak power by clock regioning
US7205614B2 (en) * 2004-01-06 2007-04-17 Faraday Technology Corp. High density ROM cell
WO2006073060A1 (en) 2004-12-16 2006-07-13 Nec Corporation Semiconductor storage device
US7570527B2 (en) * 2005-06-02 2009-08-04 Texas Instruments Incorporated Static random-access memory having reduced bit line precharge voltage and method of operating the same
US7643329B2 (en) * 2006-01-10 2010-01-05 Certichip Inc. Asymmetric four-transistor SRAM cell
US7313012B2 (en) * 2006-02-27 2007-12-25 International Business Machines Corporation Back-gate controlled asymmetrical memory cell and memory using the cell
US7298636B1 (en) 2006-03-08 2007-11-20 Integrated Device Technology, Inc. Packet processors having multi-functional range match cells therein
US7825777B1 (en) 2006-03-08 2010-11-02 Integrated Device Technology, Inc. Packet processors having comparators therein that determine non-strict inequalities between applied operands
KR101098706B1 (en) 2007-03-19 2011-12-23 후지쯔 세미컨덕터 가부시키가이샤 Semiconductor memory
US8139400B2 (en) * 2008-01-22 2012-03-20 International Business Machines Corporation Enhanced static random access memory stability using asymmetric access transistors and design structure for same
US8072797B2 (en) * 2008-07-07 2011-12-06 Certichip Inc. SRAM cell without dedicated access transistors
US8363455B2 (en) 2008-12-04 2013-01-29 David Rennie Eight transistor soft error robust storage cell
US8400802B2 (en) * 2009-11-04 2013-03-19 University-Industry Cooperation Group Of Kyunghee University Binary content addressable memory
US20110157964A1 (en) * 2009-12-30 2011-06-30 Mcpartland Richard J Memory Cell Using Leakage Current Storage Mechanism
CN101877243B (en) * 2010-04-22 2015-09-30 上海华虹宏力半导体制造有限公司 Static RAM
CN101819815B (en) * 2010-04-29 2015-05-20 上海华虹宏力半导体制造有限公司 Static random-access memory for eliminating reading interference
CN102034531A (en) * 2010-05-28 2011-04-27 上海宏力半导体制造有限公司 Static random access memory for reducing reading interference
JP2016054015A (en) * 2014-09-04 2016-04-14 株式会社東芝 Semiconductor storage device and driving method of the same
JP6441708B2 (en) * 2015-02-25 2018-12-19 ルネサスエレクトロニクス株式会社 Semiconductor memory device
US10431576B1 (en) * 2018-04-20 2019-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell array and method of manufacturing same
US11018142B2 (en) * 2018-07-16 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell and method of manufacturing the same
KR102615012B1 (en) 2018-11-12 2023-12-19 삼성전자주식회사 Memory device and operation method thereof
CN112783256B (en) * 2019-11-08 2022-06-24 奇景光电股份有限公司 Low dropout regulator based on subthreshold region
CN111899775A (en) * 2020-07-24 2020-11-06 安徽大学 SRAM memory cell circuit capable of realizing multiple logic functions and BCAM operation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0562474A (en) * 1991-08-29 1993-03-12 Nec Corp Semiconductor memory
JPH08235867A (en) * 1995-01-20 1996-09-13 Samsung Electron Co Ltd Two-transistor high-resistance load-type sram cell
JPH11260063A (en) * 1998-03-10 1999-09-24 Hitachi Ltd Semiconductor device

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3701980A (en) * 1970-08-03 1972-10-31 Gen Electric High density four-transistor mos content addressed memory
JPS5916356B2 (en) * 1977-04-30 1984-04-14 シャープ株式会社 CMOS static random access memory
JPS5475237A (en) * 1977-11-29 1979-06-15 Fujitsu Ltd Four-transistor static memory cell
JPS6076085A (en) * 1983-09-30 1985-04-30 Toshiba Corp Semiconductor memory device
JPS6124092A (en) * 1984-07-13 1986-02-01 Toshiba Corp Memory device for semiconductor
JPS61145792A (en) * 1984-12-19 1986-07-03 Matsushita Electric Ind Co Ltd Memory circuit
US4831585A (en) * 1985-11-27 1989-05-16 Massachusetts Institute Of Technology Four transistor cross-coupled bitline content addressable memory
US4694425A (en) * 1986-07-10 1987-09-15 Intel Corporation Seven transistor content addressable memory (CAM) cell
US4799192A (en) * 1986-08-28 1989-01-17 Massachusetts Institute Of Technology Three-transistor content addressable memory
US4791606A (en) * 1987-09-01 1988-12-13 Triad Semiconductors International Bv High density CMOS dynamic CAM cell
GB2243233A (en) * 1990-04-06 1991-10-23 Mosaid Inc DRAM word line driver
US5226005A (en) * 1990-11-19 1993-07-06 Unisys Corporation Dual ported content addressable memory cell and array
US5258946A (en) * 1991-02-13 1993-11-02 At&T Bell Laboratories Content-addressable memory
US5383146A (en) * 1992-06-08 1995-01-17 Music Semiconductors, Inc. Memory with CAM and RAM partitions
JPH06203580A (en) * 1992-07-16 1994-07-22 Hal Computer Syst Inc Content-addressable memory cell
JP2636159B2 (en) * 1994-01-07 1997-07-30 ハル・コンピュータ・システムズ,インコーポレイテッド Apparatus for storing "don't care" in an associative memory cell
US5396469A (en) * 1994-03-31 1995-03-07 Hewlett-Packard Company SRAM memory requiring reduced voltage swing during write
US5600598A (en) * 1994-12-14 1997-02-04 Mosaid Technologies Incorporated Memory cell and wordline driver for embedded DRAM in ASIC process
US5640342A (en) * 1995-11-20 1997-06-17 Micron Technology, Inc. Structure for cross coupled thin film transistors and static random access memory cell
DE69829539T2 (en) * 1997-11-26 2005-09-01 Texas Instruments Inc., Dallas Improvements to or at computer memories
DE69727939D1 (en) * 1997-11-28 2004-04-08 St Microelectronics Srl RAM memory cell with low power consumption and a single bit line
JPH11185474A (en) * 1997-12-17 1999-07-09 Sharp Corp Semiconductor storage device
US5973985A (en) * 1998-08-11 1999-10-26 Stmicroelectronics, Inc. Dual port SRAM cell having pseudo ground line or pseudo power line
WO2000019444A1 (en) * 1998-09-30 2000-04-06 Infineon Technologies Ag Single-port memory location
US6005790A (en) * 1998-12-22 1999-12-21 Stmicroelectronics, Inc. Floating gate content addressable memory
JPH11260055A (en) * 1998-12-25 1999-09-24 Hitachi Ltd Semiconductor device
CA2266062C (en) * 1999-03-31 2004-03-30 Peter Gillingham Dynamic content addressable memory cell
US6157558A (en) * 1999-05-21 2000-12-05 Sandisk Corporation Content addressable memory cell and array architectures having low transistor counts
US6442060B1 (en) * 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
JP4885365B2 (en) * 2000-05-16 2012-02-29 ルネサスエレクトロニクス株式会社 Semiconductor device
US6400593B1 (en) * 2001-02-08 2002-06-04 Intregrated Device Technology, Inc. Ternary CAM cell with DRAM mask circuit
CA2342575A1 (en) * 2001-04-03 2002-10-03 Mosaid Technologies Incorporated Content addressable memory cell

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0562474A (en) * 1991-08-29 1993-03-12 Nec Corp Semiconductor memory
JPH08235867A (en) * 1995-01-20 1996-09-13 Samsung Electron Co Ltd Two-transistor high-resistance load-type sram cell
JPH11260063A (en) * 1998-03-10 1999-09-24 Hitachi Ltd Semiconductor device

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
NODA K ET AL: "1.9-MUM2 LOADLESS CMOS FOUR-TRANSISTOR SRAM CELL IN A 0.18-MUM LOGIC TECHNOLOGY", SAN FRANCISCO, CA, DEC. 6 - 9, 1998,NEW YORK, NY: IEEE,US, 6 December 1998 (1998-12-06), pages 643 - 646, XP000859455, ISBN: 0-7803-4775-7 *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 387 (P - 1576) 20 July 1993 (1993-07-20) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 07 31 March 1998 (1998-03-31) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 14 22 December 1999 (1999-12-22) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007527591A (en) * 2003-06-30 2007-09-27 インテグレイテッド・デヴァイス・テクノロジー,インコーポレイテッド Memory with Ternary Search (TCAM) cell with small footprint and efficient layout aspect ratio
JP4823901B2 (en) * 2003-06-30 2011-11-24 ネットロジック・マイクロシステムズ,インコーポレイテッド Memory with Ternary Search (TCAM) cell with small footprint and efficient layout aspect ratio

Also Published As

Publication number Publication date
GB2375642A (en) 2002-11-20
KR20030014364A (en) 2003-02-17
GB2375642B (en) 2005-02-23
JP4903338B2 (en) 2012-03-28
DE10195853T1 (en) 2003-05-22
AU2001242125A1 (en) 2001-09-12
CA2299991A1 (en) 2001-09-03
CN1408118A (en) 2003-04-02
US6751111B2 (en) 2004-06-15
CN1248237C (en) 2006-03-29
KR100743808B1 (en) 2007-07-30
US20030035331A1 (en) 2003-02-20
GB0219973D0 (en) 2002-10-02
JP2003525512A (en) 2003-08-26

Similar Documents

Publication Publication Date Title
US6751111B2 (en) High density memory cell
US7106620B2 (en) Memory cell having improved read stability
US7304876B2 (en) Compare circuit for a content addressable memory cell
US7177177B2 (en) Back-gate controlled read SRAM cell
US6873532B2 (en) Content addressable memory cell having improved layout
US7821858B2 (en) eDRAM hierarchical differential sense AMP
US7492628B2 (en) Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell
US8111542B2 (en) 8T low leakage SRAM cell
US7269055B2 (en) SRAM device with reduced leakage current
JP2004525473A (en) Content addressable magnetic random access memory
US6370052B1 (en) Method and structure of ternary CAM cell in logic process
US6788566B1 (en) Self-timed read and write assist and restore circuit
JP7054012B2 (en) Semiconductor storage circuit, semiconductor storage device and data detection method
US7709299B2 (en) Hierarchical 2T-DRAM with self-timed sensing
CA2401025A1 (en) An improved high density memory cell
Mohan et al. Novel ternary storage cells and techniques for leakage reduction in ternary CAM
SRINIVAS et al. Dynamic Feedback with Control 8T Sub Threshold SRAM Cell
KR20230162331A (en) Content Addressable Memory Cell Based on Ferroelectric Transistor and Content Addressable Memory Including Same
Kandalkar et al. A 90 nm Static Random Access Memory in Submicron Technology
Bhattacharjee et al. High speedlow leakage-multi threshold 45 nm floating gated SRAM
Suganyaa et al. Operating The Sram Cell Architecture With The High Efficient And Reduced Memory Size
SWATHI et al. Low Power Area Efficient ROM Embedded SRAM Cache
Jothi et al. FinFET Based Low Power Content Addressable Memory

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2401025

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 10227380

Country of ref document: US

ENP Entry into the national phase

Ref document number: 200219973

Country of ref document: GB

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2001 564165

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020027011589

Country of ref document: KR

Ref document number: 018059961

Country of ref document: CN

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 1020027011589

Country of ref document: KR

122 Ep: pct application non-entry in european phase
RET De translation (de og part 6b)

Ref document number: 10195853

Country of ref document: DE

Date of ref document: 20030522

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 10195853

Country of ref document: DE