WO1999014664A1 - Data processing device - Google Patents
Data processing device Download PDFInfo
- Publication number
- WO1999014664A1 WO1999014664A1 PCT/US1998/018673 US9818673W WO9914664A1 WO 1999014664 A1 WO1999014664 A1 WO 1999014664A1 US 9818673 W US9818673 W US 9818673W WO 9914664 A1 WO9914664 A1 WO 9914664A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- instruction
- loop
- pipeline
- input
- unit
- Prior art date
Links
- 238000000034 method Methods 0.000 claims description 20
- 238000004364 calculation method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
Definitions
- the present invention relates to a data processing device having a pipeline structure.
- Pipeline structures are well known, and used in microprocessors and microcontrollers. To work most efficiently, a pipeline is filled up with a sequence of instructions. Once the sequence is interrupted, the pipeline is filled up again. This causes a loss of processing speed for the microprocessor. Such interrupts occur mainly when a jump, branch or loop instruction is executed, because the following instruction is often not the instruction which follows the jump, branch or loop instruction.
- Jump and branch instructions generally depend on a condition for its decision whether or not a jump or branch is to be executed.
- a loop instruction includes a parameter which indicates the number of times the loop is executed and a parameter which indicates the beginning of the loop, in particular, digital signal processors are often using loop instructions. Therefore, loop instructions can have an important influence on the resulting execution speed of a processor or a data processing unit. It is therefore an object of the present invention to provide a data processing device with means to execute loop instructions as fast as possible.
- the present invention provides, in one embodiment, a data processing device which comprises an instruction fetch unit (e.g., comprising an instruction demultiplexer) having at least an input and an output, a pipeline unit for processing data having at least input and output stages, and a loop pipeline unit for processing a loop instruction having at least input and output stages.
- the input stages of the pipeline units are connected to the output of the instruction providing unit which provides data for all pipeline units.
- the pipeline units are able to process the provided data independently in parallel.
- the loop pipeline can be a pipeline with a functionality only directed to the special loop instruction. It therefore does not necessarily need all the operating units of a regular pipeline.
- the loop pipeline handles the zero overhead loops, such that during the repetition of a loop, no branch or jump instruction and no condition testing are executed in the main pipeline.
- the loop pipeline is used to fold out the loop instruction from the execution flow allowing a loop instruction to be performed in parallel, for example, with an integer and load/store operation.
- a loop instruction cache is provided which caches the loop instruction.
- a multiplexer can be provided which supplies either the instruction sequence or the cached loop instruction to the instruction providing unit.
- a method of executing a loop comprises the steps of: if a loop instruction occurs for the first time, then the loop instruction is executed in said pipeline unit and thereby the loop related data are stored in a loop target buffer, During execution of the loop, the loop instruction is executed in the loop pipeline and the instructions included in the loop are executed in the pipeline unit in parallel. Thus, during execution of the loop no overhead occurs. In other words, the loop instruction proper never appears in the instruction pipeline unit, because it is issued in parallel with other instructions to the loop pipeline. When a loop instruction is encountered, the loop instruction is fetched and issued to the load store pipeline. However, on subsequent loop iterations the loop instruction is executed in the loop pipeline. Therefore, loops can be executed very fast with zero overhead.
- Figure 1 shows a functional block diagram of an instruction fetch module according to the present invention
- FIG. 2 shows a loop target buffer in more detail
- Figure 3 shows a loop execution unit, the loop cache buffer and the program counter update and control unit in more detail
- Figure 4 depicts a table showing the content of the pipelines during the first iteration of the loop
- Figure 5 depicts a table showing the content of the pipelines during the second and following iterations of the loop.
- Figure 6 depicts a table showing the content of the pipelines during the exit of the loop.
- the loop instructions are designed to optimize inner loops in, for example, digital signal processor algorithms, etc.
- a set of dedicated hardware is associated with the loop instructions. This set of dedicated hardware implements zero overhead loops.
- Such hardware can include an instruction fetch moduie which is an integral part of a preferred embodiment of a microcontroller and schematically shown in Figure 1.
- Figure 1 shows only the main connections between the main units.
- this instruction fetch module 1 comprises three pipeline units 10, 11 and 12.
- the microprocessor may have only one main pipeline or the main pipeline may consist of a plurality of pipelines.
- the first unit represents the integer pipeline 10 and comprises three stages, namely, a decode stage 10a, an execute stage 10b and a write back stage 10c.
- the second unit represents the load/store pipeline 11 and also comprises three stages, ⁇ ameiy, a decode stage 11a, an execute stage 11b and a write back stage 11 c.
- the third unit represents the loop pipeline 12 and comprises two stages, ⁇ ameiy, a decode/execute stage 12a and a write back stage 12c.
- An instruction demultiplexer 7, representing the instruction providing unit, provides the different pipeline units 10, 11 and 12 with their respective instructions.
- This instruction demultiplexer 7 is controlled by an issue control unit 9 which is coupled to a pipeline control unit 14.
- the instruction demultiplexer 7 is coupled to the output of a multiplexer 5 which either forwards an instruction from a cache subsystem 13 or from a loop cache buffer unit 3.
- the loop cache buffer unit 3 is coupled to a program control update and control unit 2 which is also coupled to the cache subsystem 13.
- a loop execution unit 4 is on one hand coupled to the program counter update and control unit 2 and on the other hand to the loop cache buffer 3.
- the loop cache buffer 3 can aiso contain a branch target buffer (BTB).
- BTB branch target buffer
- the output of the multiplexer 5 is connected to an input of a pre- decoder 6 which has an output which is connected to the instruction demultiplexer 7. Furthermore, the pre-decoder 6 is coupled to the program counter update and control unit 2.
- a protection register 8 is coupled to the program counter update and control unit 2 and to the three pipelines 10, 11 and 12. Further port connections between the program counter update and control unit 2 and the protection register 8 are shown in Figure 1.
- This unit 1 is responsible for feeding instructions to the different pipelines 10, 11 and 12.
- the main pipelines 10 and 11 of this embodiment have four stages.
- the first stage is formed by the instruction demultiplexer 7, the pre-decoder 6 and the logic connecting the pipelines 10, 11 and 12 with the cache subsystem 13.
- This stage is generally referred to as the fetch stage which issues the instructions to the respective main pipelines 10 and 11.
- the second stage is depicted by the units 10a and 11a and referred to as the decode stage where the instructions are decoded.
- the third stage is depicted by units 10b and 11b and referred to as the execute stage where the instructions are executed. In other words, the operation proper is performed by, for example, calculation of an address in a load/store instruction, or performing a multiplication.
- the fourth stage is depicted by units 10c and 11c and referred to as the write back stage where the results of the respective operation is written back to, for example, the register file or a memory location.
- a loop instruction whenever a loop instruction occurs for the first time, it is executed as a normal instruction in the load/store pipeline 11.
- the loop target is calculated, the new program counter is set, and the value for the loop count is loaded from a register of the register file addressed by the loop instruction.
- the loop cache buffer 3 is updated and the new loop count value is written back to the register file.
- the loop pipeline could be a fully operable pipeline which handles the complete execution of loop instructions in parallel with the other pipelines.
- Figure 2 shows the special register which is part of the loop cache buffer 3.
- a first portion 3a of the register content represents the previous instruction address.
- a second portion 3b represents the target instruction address.
- a third portion 3c represents the loop instruction size and a fourth portion 3d indicates that the entries are valid.
- the size of the address portions 3a and 3b complies with the respective address range or program counter.
- the loop instruction size portion 3c indicates the word size of the loop instruction.
- a loop instruction may be, for example, a 16 bit or a 32 bit instruction.
- the address of the following instruction will be calculated. In other words, the instruction size value will be added to the current program counter vaiue to get the address of the following instruction in the sequence. In the last pipeline stage 11c, the new value for the ioop count is written back into the respective register.
- Figure 3 shows parts of the program counter update and control unit 2, parts of loop target buffer 3, and parts of loop execution unit 4 in more detail.
- the loop target buffer 3 contains the register 3a, 3b, 3c, 3d shown in Figure 2.
- a register 3e is provided which stores the loop instruction detected during the first iteration.
- Numeral 2a depicts the program counter (PC) of the program counter update and control unit 2.
- PC program counter
- Some parts of the loop execution unit 4 are considered as to be elements of the loop pipe unit 12. These are, for example, a comparator
- the comparator 4d generates a signal which is fed to the program counter update and control unit 2. Additionally, an address comparator 4a is provided which compares the previous instruction address 3a of the loop cache buffer
- the address comparator 4a generates a signal which is fed to the program counter update and control unit 2.
- the program counter update and control unit 2 calculates and/or sets a new program counter depending on the signal of the comparators 4a and 4d. To calculate a new address or to set a new target address, the program counter update and control unit 2 gets the target instruction address from the portion
- the loop cache buffer 3 After processing the loop for the first time, the loop cache buffer 3 is set. In other words, the target address is stored in register portion 3b, the previous instruction address is stored in register portion 3a, and the loop instruction size is stored in register portion 3c. Also, register portion 3c which can be a flag, is set to indicate that the entries are valid. In addition, the loop instruction itself is stored in a register 3e which outputs its content to the multiplexer 5. This multiplexer is controlled by the output signal of the comparator 4a.
- unit 4 compares the content of the program counter 2a with the content of the register portion 3a which indicates the previous instruction address. If there is a match then the output signal of comparator 4a sets the following program counter value to the target instruction address stored in register portion 3b and the loop instruction is injected into the loop pipeline 12 from the register 3e in the loop cache buffer
- the loop instruction is not executed in the load/store pipeline 11.
- the loop pipeline 12 does not need a fetch stage, because the loop instruction is cached in register 3e during the execution of the loop.
- the first instruction or the first two instructions of the loop are executed in the integer pipeline 10 and/or the load/store pipeline 11. While this is happening, the loop instruction is executed in parallel in the loop pipeline 12.
- the loop count vaiue is fetched from the register of the register file indicated by the loop instruction.
- the loop value is then decremented by the decrementer 4c and compared to zero by the comparator 4d.
- the result of the new loop count value is written back to the respective register in the register file.
- comparator 4a If the comparator result indicates a match, a signal is sent to the program counter update and control unit 2 to indicate that this is the last time the loop is executed. Also, the flag 3d indicating a valid entry is reset. This also prevents the multiplexer 5 from being controlled further by comparator 4a. Because this happens when some instructions of the ioop are already loaded into the pipeline units, it is necessary to replace these instructions loaded into the fetch and decode stages of the pipeline units 10 and 11 with no operation instructions (NOP). Also, if comparator 4a outputs a match signal, a new target address is calculated by adding the value of loop instruction size register portion 3c to the program counter value, and this new address will be stored in the program counter. This causes the fetch stage
- the sample program contains the following sequence:
- loop_start add dO, dO, 1 ;instruction A1
- This example program contains three different kinds of instructions.
- the microcontroller of this embodiment is capable of executing up to three instructions in parallel. Two instructions can be issued in parallel with the main pipeline units 10 and 11.
- the first type load/store instructions, move data from the register file to the memory/peripherals or vice versa. Also, data can be transferred in between the register file or in between memory/peripherals.
- the second type integer instructions, process data in a definable manner, such as calculating, manipulating single bits, calculating conditions, etc.
- the integer instructions A1, A2 and N from the demonstration program are executed in the integer pipeline unit 10.
- the load/store instructions L1 and L2 from the demonstration program are executed in the load/store pipeline unit 11.
- an instruction pair (a load/store instruction and a integer instruction) are always issued to the pipelines 10 and 1 in parallel. In other words, two instructions of the same type never follow each other.
- the above mentioned demonstration program shows such an arrangement. If two instructions of the same kind have to follow each other, a no operation instruction (NOP) is issued to the respective other pipeline unit.
- the third pipeline 12 can only execute one type of instruction, namely the loop instruction B.
- the instruction B is kind of a load/store instruction. Therefore, it is executed either in the load/store pipeline unit 11 or the loop pipeline unit 12.
- Figure 4 shows a table with the first iteration of the loop.
- the numerals A1 , AZ, L1 , L2, B and N indicate the instructions issued to the pipeline, whereas a_"-" indicates a no operation instruction (NOP).
- NOP no operation instruction
- instructions A1 and L1 are in the decode stages 10b and 11b, and instructions A2 and L2 are in the fetch stages 10a and 11a, respectively.
- the instructions A1 and L1 are forwarded to the execution stages 10c and 11 c and the loop instruction B is issued for the first time to the load/store pipeline stage 11a and the following instruction N is issued to the fetch stage 10a.
- the ioop instruction B is decoded and a new program counter containing the target loop address (loop_start) is calculated.
- no operation instructions replace the decode and fetch stage contents of the integer pipeline and the fetch stage of the load/store pipeline.
- the new program counter results in an issue of instructions A1 and L1 to the respective fetch stages of the integer and the load/store pipelines 10, 11.
- the loop target buffer is updated as described above.
- Figure 5 shows the second and subsequent iterations of the loop.
- the loop body consisting of instructions A1 , L1 , JA2, and L2, is executed normally until the instruction or instruction pair prior to the loop is fetched and the address in PC 2 matches the address stored in the register portion 3a of the loop target buffer 3.
- the loop target address is read from register portion 3b of the loop cache buffer 3 and is used as the new address in PC 2.
- the loop target instructions are fetched on the following cycle and are issued to the decode stage along with the cached loop instruction which is issued to the loop pipeline 12 in cycie C7, C9, etc.
- the loop is then executed in the decode phase using the comparator 4d and the decrementer 4c.
- the actual program counter is compared to the address of the instruction A2, which represents the last instruction pair before the loop instruction B.
- Any other address in between the loop can be used for this purpose.
- the beginning address of the loop (loop_start) could be used for triggering the issue of the loop instruction.
- using the instruction address before the loop instruction has the advantage that, when the loop instruction is executed from the register 3e of loop target buffer 3, the loop instruction is injected with the target instruction and is therefore the oldest instruction in the pipeline. Thus, no additional means for handling exception routines are necessary.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69809450T DE69809450T2 (en) | 1997-09-12 | 1998-09-04 | COMPUTING DEVICE |
IL13445998A IL134459A0 (en) | 1997-09-12 | 1998-09-04 | Data processing device |
JP2000512133A JP2001517819A (en) | 1997-09-12 | 1998-09-04 | Data processing device |
KR1020007002609A KR20010030587A (en) | 1997-09-12 | 1998-09-04 | Data processing device |
EP98946886A EP1012705B1 (en) | 1997-09-12 | 1998-09-04 | Data processing device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/928,444 | 1997-09-12 | ||
US08/928,444 US6085315A (en) | 1997-09-12 | 1997-09-12 | Data processing device with loop pipeline |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999014664A1 true WO1999014664A1 (en) | 1999-03-25 |
Family
ID=25456239
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/018673 WO1999014664A1 (en) | 1997-09-12 | 1998-09-04 | Data processing device |
Country Status (7)
Country | Link |
---|---|
US (1) | US6085315A (en) |
EP (1) | EP1012705B1 (en) |
JP (1) | JP2001517819A (en) |
KR (1) | KR20010030587A (en) |
DE (1) | DE69809450T2 (en) |
IL (1) | IL134459A0 (en) |
WO (1) | WO1999014664A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001005660A (en) * | 1999-05-26 | 2001-01-12 | Infineon Technol North America Corp | Method and device for reducing instruction transaction in microprocessor |
Families Citing this family (94)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002532775A (en) * | 1998-12-08 | 2002-10-02 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Interpreter program execution method |
WO2000055724A1 (en) * | 1999-03-17 | 2000-09-21 | Infineon Technologies Ag | Caching of short program loops in an instruction fifo |
EP1039375A1 (en) * | 1999-03-19 | 2000-09-27 | Motorola, Inc. | Method and apparatus for implementing zero overhead loops |
US6598155B1 (en) * | 2000-01-31 | 2003-07-22 | Intel Corporation | Method and apparatus for loop buffering digital signal processing instructions |
US6963965B1 (en) * | 1999-11-30 | 2005-11-08 | Texas Instruments Incorporated | Instruction-programmable processor with instruction loop cache |
US7302557B1 (en) * | 1999-12-27 | 2007-11-27 | Impact Technologies, Inc. | Method and apparatus for modulo scheduled loop execution in a processor architecture |
US6732203B2 (en) | 2000-01-31 | 2004-05-04 | Intel Corporation | Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus |
US6918028B1 (en) * | 2000-03-28 | 2005-07-12 | Analog Devices, Inc. | Pipelined processor including a loosely coupled side pipe |
US6757817B1 (en) * | 2000-05-19 | 2004-06-29 | Intel Corporation | Apparatus having a cache and a loop buffer |
US7065636B2 (en) * | 2000-12-20 | 2006-06-20 | Intel Corporation | Hardware loops and pipeline system using advanced generation of loop parameters |
US6842895B2 (en) * | 2000-12-21 | 2005-01-11 | Freescale Semiconductor, Inc. | Single instruction for multiple loops |
TW567695B (en) * | 2001-01-17 | 2003-12-21 | Ibm | Digital baseband system |
JP2002229779A (en) * | 2001-02-02 | 2002-08-16 | Mitsubishi Electric Corp | Information processor |
US6950929B2 (en) * | 2001-05-24 | 2005-09-27 | Samsung Electronics Co., Ltd. | Loop instruction processing using loop buffer in a data processing device having a coprocessor |
US7249248B2 (en) * | 2002-11-25 | 2007-07-24 | Intel Corporation | Method, apparatus, and system for variable increment multi-index looping operations |
US7159103B2 (en) * | 2003-03-24 | 2007-01-02 | Infineon Technologies Ag | Zero-overhead loop operation in microprocessor having instruction buffer |
DE102005001679B4 (en) * | 2005-01-13 | 2008-11-13 | Infineon Technologies Ag | Microprocessor device, and method for branch prediction for conditional branch instructions in a microprocessor device |
US7711934B2 (en) * | 2005-10-31 | 2010-05-04 | Mips Technologies, Inc. | Processor core and method for managing branch misprediction in an out-of-order processor pipeline |
US7734901B2 (en) * | 2005-10-31 | 2010-06-08 | Mips Technologies, Inc. | Processor core and method for managing program counter redirection in an out-of-order processor pipeline |
US7873820B2 (en) * | 2005-11-15 | 2011-01-18 | Mips Technologies, Inc. | Processor utilizing a loop buffer to reduce power consumption |
US7562191B2 (en) * | 2005-11-15 | 2009-07-14 | Mips Technologies, Inc. | Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme |
US7496771B2 (en) * | 2005-11-15 | 2009-02-24 | Mips Technologies, Inc. | Processor accessing a scratch pad on-demand to reduce power consumption |
US7721071B2 (en) * | 2006-02-28 | 2010-05-18 | Mips Technologies, Inc. | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor |
US20070204139A1 (en) | 2006-02-28 | 2007-08-30 | Mips Technologies, Inc. | Compact linked-list-based multi-threaded instruction graduation buffer |
EP2477109B1 (en) | 2006-04-12 | 2016-07-13 | Soft Machines, Inc. | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations |
US7370178B1 (en) * | 2006-07-14 | 2008-05-06 | Mips Technologies, Inc. | Method for latest producer tracking in an out-of-order processor, and applications thereof |
US20080016326A1 (en) * | 2006-07-14 | 2008-01-17 | Mips Technologies, Inc. | Latest producer tracking in an out-of-order processor, and applications thereof |
US7650465B2 (en) | 2006-08-18 | 2010-01-19 | Mips Technologies, Inc. | Micro tag array having way selection bits for reducing data cache access power |
US7657708B2 (en) * | 2006-08-18 | 2010-02-02 | Mips Technologies, Inc. | Methods for reducing data cache access power in a processor using way selection bits |
US8032734B2 (en) * | 2006-09-06 | 2011-10-04 | Mips Technologies, Inc. | Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor |
US7647475B2 (en) * | 2006-09-06 | 2010-01-12 | Mips Technologies, Inc. | System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue |
US7594079B2 (en) | 2006-09-29 | 2009-09-22 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
US9946547B2 (en) | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
US20080082793A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Detection and prevention of write-after-write hazards, and applications thereof |
US8078846B2 (en) | 2006-09-29 | 2011-12-13 | Mips Technologies, Inc. | Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated |
EP2527972A3 (en) | 2006-11-14 | 2014-08-06 | Soft Machines, Inc. | Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes |
US7987347B2 (en) * | 2006-12-22 | 2011-07-26 | Broadcom Corporation | System and method for implementing a zero overhead loop |
US7991985B2 (en) * | 2006-12-22 | 2011-08-02 | Broadcom Corporation | System and method for implementing and utilizing a zero overhead loop |
KR100861073B1 (en) * | 2007-01-23 | 2008-10-01 | 충북대학교 산학협력단 | Parallel processing processor architecture adapting adaptive pipeline |
ATE463788T1 (en) * | 2007-06-26 | 2010-04-15 | Ericsson Telefon Ab L M | DATA PROCESSING UNIT FOR NESTED LOOP INSTRUCTIONS |
US20090109996A1 (en) * | 2007-10-29 | 2009-04-30 | Hoover Russell D | Network on Chip |
US20090125706A1 (en) * | 2007-11-08 | 2009-05-14 | Hoover Russell D | Software Pipelining on a Network on Chip |
US20090125703A1 (en) * | 2007-11-09 | 2009-05-14 | Mejdrich Eric O | Context Switching on a Network On Chip |
US8261025B2 (en) * | 2007-11-12 | 2012-09-04 | International Business Machines Corporation | Software pipelining on a network on chip |
US8526422B2 (en) * | 2007-11-27 | 2013-09-03 | International Business Machines Corporation | Network on chip with partitions |
US7917703B2 (en) * | 2007-12-13 | 2011-03-29 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidate commands |
US8473667B2 (en) * | 2008-01-11 | 2013-06-25 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidation messages |
US8010750B2 (en) * | 2008-01-17 | 2011-08-30 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidate commands |
US8018466B2 (en) * | 2008-02-12 | 2011-09-13 | International Business Machines Corporation | Graphics rendering on a network on chip |
US7913010B2 (en) * | 2008-02-15 | 2011-03-22 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
US8490110B2 (en) * | 2008-02-15 | 2013-07-16 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
US20090245257A1 (en) * | 2008-04-01 | 2009-10-01 | International Business Machines Corporation | Network On Chip |
US20090260013A1 (en) * | 2008-04-14 | 2009-10-15 | International Business Machines Corporation | Computer Processors With Plural, Pipelined Hardware Threads Of Execution |
US20090271172A1 (en) * | 2008-04-24 | 2009-10-29 | International Business Machines Corporation | Emulating A Computer Run Time Environment |
US8078850B2 (en) * | 2008-04-24 | 2011-12-13 | International Business Machines Corporation | Branch prediction technique using instruction for resetting result table pointer |
US8423715B2 (en) * | 2008-05-01 | 2013-04-16 | International Business Machines Corporation | Memory management among levels of cache in a memory hierarchy |
US8494833B2 (en) * | 2008-05-09 | 2013-07-23 | International Business Machines Corporation | Emulating a computer run time environment |
US20090282419A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines Corporation | Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip |
US8392664B2 (en) * | 2008-05-09 | 2013-03-05 | International Business Machines Corporation | Network on chip |
US8020168B2 (en) * | 2008-05-09 | 2011-09-13 | International Business Machines Corporation | Dynamic virtual software pipelining on a network on chip |
US7991978B2 (en) * | 2008-05-09 | 2011-08-02 | International Business Machines Corporation | Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor |
US7958340B2 (en) * | 2008-05-09 | 2011-06-07 | International Business Machines Corporation | Monitoring software pipeline performance on a network on chip |
US7861065B2 (en) * | 2008-05-09 | 2010-12-28 | International Business Machines Corporation | Preferential dispatching of computer program instructions |
US20090282211A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines | Network On Chip With Partitions |
US8214845B2 (en) * | 2008-05-09 | 2012-07-03 | International Business Machines Corporation | Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data |
US8040799B2 (en) * | 2008-05-15 | 2011-10-18 | International Business Machines Corporation | Network on chip with minimum guaranteed bandwidth for virtual communications channels |
US8230179B2 (en) * | 2008-05-15 | 2012-07-24 | International Business Machines Corporation | Administering non-cacheable memory load instructions |
US8438578B2 (en) * | 2008-06-09 | 2013-05-07 | International Business Machines Corporation | Network on chip with an I/O accelerator |
US8195884B2 (en) * | 2008-09-18 | 2012-06-05 | International Business Machines Corporation | Network on chip with caching restrictions for pages of computer memory |
US9170816B2 (en) * | 2009-01-15 | 2015-10-27 | Altair Semiconductor Ltd. | Enhancing processing efficiency in large instruction width processors |
US8966228B2 (en) * | 2009-03-20 | 2015-02-24 | Arm Limited | Instruction fetching following changes in program flow |
JP5423156B2 (en) * | 2009-06-01 | 2014-02-19 | 富士通株式会社 | Information processing apparatus and branch prediction method |
EP2616928B1 (en) * | 2010-09-17 | 2016-11-02 | Soft Machines, Inc. | Single cycle multi-branch prediction including shadow cache for early far branch prediction |
EP2689326B1 (en) | 2011-03-25 | 2022-11-16 | Intel Corporation | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines |
EP2689327B1 (en) | 2011-03-25 | 2021-07-28 | Intel Corporation | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines |
WO2012162188A2 (en) | 2011-05-20 | 2012-11-29 | Soft Machines, Inc. | Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines |
CN103649931B (en) | 2011-05-20 | 2016-10-12 | 索夫特机械公司 | For supporting to be performed the interconnection structure of job sequence by multiple engines |
KR101703401B1 (en) | 2011-11-22 | 2017-02-06 | 소프트 머신즈, 인크. | An accelerated code optimizer for a multiengine microprocessor |
KR101832679B1 (en) | 2011-11-22 | 2018-02-26 | 소프트 머신즈, 인크. | A microprocessor accelerated code optimizer |
US9569211B2 (en) | 2012-08-03 | 2017-02-14 | International Business Machines Corporation | Predication in a vector processor |
US9632777B2 (en) | 2012-08-03 | 2017-04-25 | International Business Machines Corporation | Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry |
US9575755B2 (en) * | 2012-08-03 | 2017-02-21 | International Business Machines Corporation | Vector processing in an active memory device |
US9594724B2 (en) | 2012-08-09 | 2017-03-14 | International Business Machines Corporation | Vector register file |
US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
KR102063656B1 (en) | 2013-03-15 | 2020-01-09 | 소프트 머신즈, 인크. | A method for executing multithreaded instructions grouped onto blocks |
KR20150130510A (en) | 2013-03-15 | 2015-11-23 | 소프트 머신즈, 인크. | A method for emulating a guest centralized flag architecture by using a native distributed flag architecture |
US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
WO2023049422A2 (en) * | 2021-09-26 | 2023-03-30 | Ceremorphic, Inc | Core processor and redundant branch processor with control flow attack detection |
US11921843B2 (en) | 2021-09-26 | 2024-03-05 | Ceremorphic, Inc. | Multi-threaded secure processor with control flow attack detection |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3593306A (en) * | 1969-07-25 | 1971-07-13 | Bell Telephone Labor Inc | Apparatus for reducing memory fetches in program loops |
US5131086A (en) * | 1988-08-25 | 1992-07-14 | Edgcore Technology, Inc. | Method and system for executing pipelined three operand construct |
EP0623874A1 (en) * | 1993-05-03 | 1994-11-09 | International Business Machines Corporation | Method for improving the performance of processors executing instructions in a loop |
US5485629A (en) * | 1993-01-22 | 1996-01-16 | Intel Corporation | Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines |
EP0742518A2 (en) * | 1995-05-12 | 1996-11-13 | Matsushita Electric Industrial Co., Ltd. | Compiler and processor for processing loops at high speed |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4626988A (en) * | 1983-03-07 | 1986-12-02 | International Business Machines Corporation | Instruction fetch look-aside buffer with loop mode control |
US4566063A (en) * | 1983-10-17 | 1986-01-21 | Motorola, Inc. | Data processor which can repeat the execution of instruction loops with minimal instruction fetches |
FR2557712B1 (en) * | 1983-12-30 | 1988-12-09 | Trt Telecom Radio Electr | PROCESSOR FOR PROCESSING DATA BASED ON INSTRUCTIONS FROM A PROGRAM MEMORY |
JPH0475139A (en) * | 1990-07-18 | 1992-03-10 | Toshiba Corp | Loop parallelizing system |
JP3032031B2 (en) * | 1991-04-05 | 2000-04-10 | 株式会社東芝 | Loop optimization method and apparatus |
US5898882A (en) * | 1993-01-08 | 1999-04-27 | International Business Machines Corporation | Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage |
JPH06243036A (en) * | 1993-02-12 | 1994-09-02 | Hitachi Ltd | Cache control system |
US5809308A (en) * | 1995-11-17 | 1998-09-15 | Sun Microsystems, Inc. | Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler |
-
1997
- 1997-09-12 US US08/928,444 patent/US6085315A/en not_active Expired - Lifetime
-
1998
- 1998-09-04 KR KR1020007002609A patent/KR20010030587A/en not_active Application Discontinuation
- 1998-09-04 JP JP2000512133A patent/JP2001517819A/en active Pending
- 1998-09-04 IL IL13445998A patent/IL134459A0/en unknown
- 1998-09-04 WO PCT/US1998/018673 patent/WO1999014664A1/en not_active Application Discontinuation
- 1998-09-04 DE DE69809450T patent/DE69809450T2/en not_active Expired - Lifetime
- 1998-09-04 EP EP98946886A patent/EP1012705B1/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3593306A (en) * | 1969-07-25 | 1971-07-13 | Bell Telephone Labor Inc | Apparatus for reducing memory fetches in program loops |
US5131086A (en) * | 1988-08-25 | 1992-07-14 | Edgcore Technology, Inc. | Method and system for executing pipelined three operand construct |
US5485629A (en) * | 1993-01-22 | 1996-01-16 | Intel Corporation | Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines |
EP0623874A1 (en) * | 1993-05-03 | 1994-11-09 | International Business Machines Corporation | Method for improving the performance of processors executing instructions in a loop |
EP0742518A2 (en) * | 1995-05-12 | 1996-11-13 | Matsushita Electric Industrial Co., Ltd. | Compiler and processor for processing loops at high speed |
Non-Patent Citations (2)
Title |
---|
"BRANCH BUFFERING", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 36, no. 5, 1 May 1993 (1993-05-01), pages 129 - 131, XP000408936 * |
R.G. WEDIG AND M.A. ROSE: "The reduction of branch instruction execution overhead using structured control flow", 11TH INTERNATIONSL SYMPOSIUM ON COMPUTER ARCHITECTURE, 5 June 1984 (1984-06-05) - 7 June 1984 (1984-06-07), ann arbor,mi,us, pages 119 - 125, XP000212034 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001005660A (en) * | 1999-05-26 | 2001-01-12 | Infineon Technol North America Corp | Method and device for reducing instruction transaction in microprocessor |
Also Published As
Publication number | Publication date |
---|---|
US6085315A (en) | 2000-07-04 |
KR20010030587A (en) | 2001-04-16 |
JP2001517819A (en) | 2001-10-09 |
DE69809450T2 (en) | 2003-07-03 |
IL134459A0 (en) | 2001-04-30 |
EP1012705A1 (en) | 2000-06-28 |
EP1012705B1 (en) | 2002-11-13 |
DE69809450D1 (en) | 2002-12-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6085315A (en) | Data processing device with loop pipeline | |
US5051885A (en) | Data processing system for concurrent dispatch of instructions to multiple functional units | |
US4648034A (en) | Busy signal interface between master and slave processors in a computer system | |
EP2519874B1 (en) | Branching processing method and system | |
JP3842474B2 (en) | Data processing device | |
US6289445B2 (en) | Circuit and method for initiating exception routines using implicit exception checking | |
US20050149706A1 (en) | Efficient link and fall-through address calculation | |
WO2000068784A1 (en) | Data processing device, method for executing load or store instructions and method for compiling programs | |
IE990754A1 (en) | An apparatus for software initiated prefetch and method therefor | |
US5454087A (en) | Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT | |
US11816485B2 (en) | Nested loop control | |
US5313644A (en) | System having status update controller for determining which one of parallel operation results of execution units is allowed to set conditions of shared processor status word | |
EP0772821A1 (en) | Tagged prefetch and instruction decoder for variable length instruction set and method of operation | |
US11442709B2 (en) | Nested loop control | |
JPH01214932A (en) | Data processor | |
EP1050811A1 (en) | Branching in a computer system | |
WO2004072848A9 (en) | Method and apparatus for hazard detection and management in a pipelined digital processor | |
US6115730A (en) | Reloadable floating point unit | |
JP4613168B2 (en) | Instruction alignment method and apparatus | |
US7020769B2 (en) | Method and system for processing a loop of instructions | |
JP5238960B2 (en) | Method and apparatus for reducing instruction transactions in a microprocessor | |
US6654872B1 (en) | Variable length instruction alignment device and method | |
EP3559803A1 (en) | Vector generating instruction | |
US5838961A (en) | Method of operation and apparatus for optimizing execution of short instruction branches | |
JP3100705B2 (en) | Apparatus for instruction preparation in a microprocessor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 134459 Country of ref document: IL |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): IL JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1998946886 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 2000 512133 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020007002609 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 1998946886 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1020007002609 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1998946886 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1020007002609 Country of ref document: KR |