US20070076461A1 - Bitcell layout - Google Patents
Bitcell layout Download PDFInfo
- Publication number
- US20070076461A1 US20070076461A1 US11/241,390 US24139005A US2007076461A1 US 20070076461 A1 US20070076461 A1 US 20070076461A1 US 24139005 A US24139005 A US 24139005A US 2007076461 A1 US2007076461 A1 US 2007076461A1
- Authority
- US
- United States
- Prior art keywords
- transistors
- storage cell
- line
- read channel
- cell region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 210000000352 storage cell Anatomy 0.000 claims abstract description 61
- 230000015654 memory Effects 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 description 21
- 239000002184 metal Substances 0.000 description 11
- 238000013461 design Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000008520 organization Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
Definitions
- design rules for single layer polysilicon device layout may include limitations including, but not necessarily limited to, the routing, spacing, width, and length of wiring lines, vias, interconnects, and other structures formed in the electronic device.
- Such design rules are typically imposed to obtain devices having the desired specifications for area, timing, power, and yield.
- to enhance certain specifications often leads to degradation of other specifications.
- decreasing area may lead to decreased yield due to processing difficulties caused by the decreased area.
- a balancing of the various specifications is carried out to obtain acceptable devices. This is particularly so for process technologies in the sub-100 nm region.
- bitcell is known in the art as a 1R+1W bitcell design (where R stands for read and W stands for write).
- R stands for read and W stands for write
- Such a bitcell is often used as a multi-port memory (for example, as a register file) bitcell in integrated circuit design.
- the IR section is known as the read channel section of the bitcell
- the 1W section is known as the storage cell section of the bitcell.
- the transistors may have different sizes, and due to the asymmetry in the transistors within the cell and the imposition of design rules such as discussed above, it is difficult to create an efficient, compact bitcell layout.
- the 1R+1W bitcell may have a 6T+2T configuration (6transistor+2transistor), with 6 transistors in the storage cell section and 2 transistors in the read channel section.
- a generalized bitcell structure 10 is illustrated in FIG. 1 , in which the transistors in the storage cell section 12 are clustered together and then the transistors in the read channel section 14 are clustered together in an adjoining area to the side of the entire storage cell section 12 .
- FIG. 1 illustrates a generalized layout of a storage cell section and a read section of a bitcell
- FIG. 2 illustrates an electrical schematic of a bitcell, in accordance with certain embodiments
- FIG. 3 illustrates a top view layout of a bitcell having a storage cell section and a read section, in accordance with certain embodiments
- FIG. 4 illustrates a top view layout of a bitcell including the relative position of the transistors within the storage cell section and the read section, in accordance with certain embodiments
- FIG. 5 illustrates a top view of certain layers in a bitcell having a transistor layout similar to that illustrated in FIG. 4 , in accordance with certain embodiments.
- FIG. 6 illustrates an electronic system arrangement in which embodiments may find application.
- FIG. 2 is a schematic of electrical connections for a bitcell such as a register file bitcell, having eight transistors.
- the schematic in FIG. 2 illustrates the electrical connections and not the actual physical layout (spacing, size, etc.) of the transistors. Such electrical connections may be used in certain embodiments described herein.
- FIG. 2 illustrates six transistors T 1 -T 6 of the storage cell section, and two transistors T 7 -T 8 of the read channel section.
- the transistors may be conventional field effect transistors including a'gate and source/drain regions.
- At the top of FIG. 2 are the read word line (rdwl) and the write word line (wrwl).
- Coupled to the transistor T 5 is the data in (di) line and coupled to transistor T 6 is the data in bar (dib) line. Coupled to transistor T 8 is the read out (ro) line. Nodes (n 1 and n 2 ), power (vcc), and ground (vss) lines are also shown.
- the 6T+2T organization can be readily observed.
- the 2T read channel section may use larger transistors than the 6T storage cell section, for good read performance. It should be noted that the storage cell transistors may also vary in size, according to standard memory cell design practice.
- Certain embodiments described herein relate to an efficient, compact layout of a bitcell.
- a bitcell may in certain embodiments be used as a register file bitcell.
- the layout reconfigures the transistors away from the known organization of clustering the storage cell section and then appending the read channel section to the side of the entire storage cell section as in FIG. 1 . Instead, the storage cell section extends around part of the read channel section to shorten signal paths and improve area efficiency. As a result, this cell is more compact and has an improved density.
- this bitcell is arrayed out, a relatively regular and uniform pattern is obtained, which is advantageous for manufacturability.
- FIG. 3 One example of such a bitcell layout is illustrated in FIG. 3 .
- FIG. 3 illustrates a top view bitcell layout 20 including the relative positions of the storage cell section and the read channel section.
- the storage cell section 22 is wrapped around a portion of the read channel section 24 , in order to shorten signal paths and improve area efficiency.
- This layout leads to superior density for memories utilizing such a 1R+1W bitcell.
- the storage cell section 22 as illustrated in FIG. 3 has a substantially L-shaped arrangement.
- the read channel section 24 as illustrated in FIG. 3 has a substantially rectangular shape that fits into the open region defined by the L shape of the storage cell section.
- a dimension x 2 of the storage cell section 22 is greater than a dimension x 1 of the read channel section 24
- a dimension y 2 of the storage cell section 22 is greater than a dimension y 1 of the read channel section 24 .
- FIG. 4 illustrates an example of an embodiment of a bitcell 30 showing the relative locations of the transistors, with the transistors being positioned in a storage cell section 32 and the read channel section 34 similar to those illustrated in FIG. 3 . More specifically, as illustrated in FIG. 4 , two transistors, T 3 and T 2 , are positioned in an upper portion of the L-shaped storage cell section 32 . Two transistors, T 4 and T 1 , are positioned in a lower portion of the L-shaped storage cell section 32 . At least a portion of each of transistors T 1 and T 2 is positioned along a line (in a vertical direction as illustrated in FIG.
- each of transistors T 1 and T 4 is positioned along a line (in a horizontal direction as illustrated in FIG. 4 ).
- at least a portion of each of transistors T 4 and T 3 is positioned along a line (in a vertical direction as illustrated in FIG. 4 ).
- the transistors T 6 and T 5 are positioned in a lower right hand portion of the L-shaped storage cell section. At least a portion of each of the transistors T 6 and T 5 is positioned along the same line (in a horizontal direction as illustrated in FIG. 4 ) as transistors T 1 and T 4 .
- Read channel region 34 includes transistors T 7 and T 8 , with at least a portion of transistor T 7 positioned along the same line (in a horizontal direction as illustrated in FIG. 4 ) as transistors T 3 and T 2 .
- transistors T 7 and T 8 are positioned along a line (in a vertical direction as illustrated in FIG. 4 ) with transistor T 6 .
- the lines described above as in a horizontal direction are orthogonal to the lines described above as in a vertical direction
- the lines in the horizontal direction are parallel to each other
- the lines in the vertical direction are parallel to each other.
- the transistors may be positioned along lines that intersect at angles other than orthogonal or parallel.
- Certain embodiments may also include bitcells having more or less than 8 transistors, having a similar layout with a substantially L-shaped storage cell section and a read channel region that fits together with the storage cell section in a manner such as that shown in FIG. 3 , for example.
- certain embodiments when viewed from above, may also be described as having a 2 ⁇ 2 array including transistors positioned in each of an upper left, upper right, lower left, and lower right portion of the 2 ⁇ 2 array.
- the embodiment illustrated in FIG. 4 includes at least part of transistors T 7 and T 8 in the upper right portion, transistors T 3 and T 2 in the upper left portion, transistors T 4 and Ti in the lower left portion, and transistors T 6 and T 5 in the lower right portion of the 2 ⁇ 2 array.
- FIG. 5 illustrates a more detailed view of a bitcell structure 100 having a transistor layout similar to that of FIG. 4 , including various layers in the structure in accordance with one embodiment.
- the view illustrated in FIG. 5 omits certain layers known to be included in transistor structures in known locations, including, but not necessarily limited to, gate oxide layer, oxide spacers, and interlayer dielectric.
- FIG. 5 also shows the relative location of the eight transistors as seen in FIG. 4 .
- the bitcell of FIG. 5 has a 6T+2T structure with electrical connections such as those illustrated in FIG. 2 .
- the bitcell structure 100 includes a semiconductor substrate 102 having an n-well region 104 implanted therein.
- the substrate also includes diffusion regions 105 .
- the n-well region 104 is bounded by small dotted lines.
- the diffusion regions 105 are bounded by alternating longer and shorter dashed lines, with seven diffusion regions 105 illustrated in FIG. 5 .
- FIG. 5 illustrates four polysilicon gate layer regions 106 , bounded by alternating dotted and dashed lines. Nodes n 1 and n 2 are also shown.
- First metal layer regions 108 and second metal layer regions 110 are also illustrated, with the first metal layer regions 108 bounded by dashed lines and the second metal layer regions 110 bounded by solid lines.
- the second metal layer regions 110 include power (vcc), ground (vss), read out (ro), data in (di), and data in bar (dib) lines.
- a plurality of contact vias between various of the layers are also present in FIG. 5 .
- Contact vias 112 are formed between the diffusion regions 105 in the semiconductor substrate 102 and the first metal layer regions 108 , or between the polysilicon regions 106 and the first metal layer regions 108 , with the contact vias 112 being bounded by short dashed lines.
- Contact vias 118 are formed between first metal layer regions 108 and second metal layer regions 110 , with the contact vias 118 being bounded by short dashed lines.
- Contact vias 120 are formed between second metal layer regions 110 and third metal layer regions (not shown), with the contact vias 120 being bounded by solid lines.
- the relative positions of the transistors T 1 -T 8 are also illustrated in FIG. 5 .
- the labels T 1 -T 8 are positioned over the gate portion of the transistor.
- Transistors T 3 , T 2 , and T 7 are positioned so that a line (in the horizontal direction as illustrated in FIG. 5 ) contacts at least part of each of these transistors.
- transistors T 4 , T 1 , T 6 , and T 5 are positioned so that a line (in the horizontal direction as illustrated in FIG. 5 ) contacts at least part of each of these transistors.
- the transistors T 5 and T 6 may be slightly larger than the other storage cell transistors (T 1 -T 4 ).
- the transistors T 3 and T 4 are positioned so that a line (in the vertical direction as illustrated in FIG. 5 ) contacts at least part of each of these transistors.
- the transistors T 2 and T 1 are also positioned so that a line (in the vertical direction as illustrated in FIG. 5 ) contacts at least part of each of these transistors.
- the transistors T 7 , T 8 , and T 6 are also positioned so that a line (in the vertical direction as illustrated in FIG. 5 ) contacts at least part of each of these transistors.
- Certain embodiments utilize arrays of bitcells having a structure such as that illustrated in FIG. 5 , to form, for example, memory such as RAM (random access memory) that is used as a register file.
- memory such as RAM (random access memory)
- RAM random access memory
- the bitcell pattern is relatively uniform and regular, which is advantageous for manufacturing and for predicting performance.
- bitcell layout may include memories for a variety of chip designs including, but not limited to, processors, chipsets, ASIC's (application specific integrated circuits), and SOC's (system on a chip). Embodiments are applicable for advanced process technologies of the sub-100 nm region, including 90 nm and below.
- Embodiments may also relate to methods for forming a bitcell.
- a plurality of transistors in a storage cell section may be positioned in a substantially L-shaped arrangement, for example, the arrangement illustrated in FIGS. 3-5 .
- a plurality of transistors in a read channel section are positioned within the region defined by the L-shape of the storage cell section, so that together the storage cell section and the read cell section are formed to have a substantially rectangular shape.
- FIG. 6 schematically illustrates one example of an electronic system environment in which aspects of described embodiments may be embodied. Other embodiments need not include all of the features specified in FIG. 6 , and may include alternative features not specified in FIG. 6 .
- the system 201 of FIG. 6 may include at least one central processing unit (CPU) 203 .
- the CPU 203 also referred to as a microprocessor, may be attached to an integrated circuit package 205 , which is then coupled to a printed circuit board 207 , which in this embodiment, may be a motherboard.
- the CPU 203 is an example of an electronic device that may include a plurality of bitcells (such as register file bitcells) having a structure in accordance with embodiments such as described above and illustrated in FIGS. 3-5 .
- the system 201 further may further include memory 209 and one or more controllers 211 a , 211 b . . . 211 n , which are also disposed on the motherboard 207 .
- the motherboard 207 may be a single layer or multi-layered board which has a plurality of conductive lines that provide communication between the circuits in the package 205 and other components mounted to the board 207 .
- one or more of the CPU 203 , memory 209 and controllers 211 a , 211 b . . . 211 n may be disposed on other cards such as daughter cards or expansion cards.
- the CPU 203 , memory 209 and controllers 211 a , 211 b . . . 211 n may each be seated in individual sockets or may be connected directly to a printed circuit board.
- a display 215 may also be included.
- the system 201 may comprise any suitable computing device, including, but not limited to, a mainframe, server, personal computer, workstation, laptop, handheld computer, handheld gaming device, handheld entertainment device (for example, an MP3 (moving picture experts group layer-3 audio) player), PDA (personal digital assistant) telephony device (wireless or wired), network appliance, virtualization device, storage controller, network controller, etc.
- a mainframe server, personal computer, workstation, laptop, handheld computer, handheld gaming device, handheld entertainment device (for example, an MP3 (moving picture experts group layer-3 audio) player), PDA (personal digital assistant) telephony device (wireless or wired), network appliance, virtualization device, storage controller, network controller, etc.
- MP3 moving picture experts group layer-3 audio
- PDA personal digital assistant
- the controllers 211 a , 211 b . . . 211 n may include a system controller, peripheral controller, memory controller, hub controller, I/O (input/output) bus controller, video controller, network controller, storage controller, communications controller, etc.
- a storage controller can control the reading of data from and the writing of data to the storage 213 in accordance with a storage protocol layer.
- the storage protocol of the layer may be any of a number of known storage protocols. Data being written to or read from the storage 213 may be cached in accordance with known caching techniques.
- a network controller can include one or more protocol layers to send and receive network packets to and from remote devices over a network 217 .
- the network 217 may comprise a Local Area Network (LAN), the Internet, a Wide Area Network (WAN), Storage Area Network (SAN), etc. Embodiments may be configured to transmit and receive data over a wireless network or connection.
- the network controller and various protocol layers may employ the Ethernet protocol over unshielded twisted pair cable, token ring protocol, Fibre Channel protocol, etc., or any other suitable network communication protocol.
Abstract
Description
- As electronic devices continue to shrink, advanced process technologies place severe restrictions on transistor layout to ensure manufacturability and performance. For example, design rules for single layer polysilicon device layout may include limitations including, but not necessarily limited to, the routing, spacing, width, and length of wiring lines, vias, interconnects, and other structures formed in the electronic device. Such design rules are typically imposed to obtain devices having the desired specifications for area, timing, power, and yield. Unfortunately, to enhance certain specifications often leads to degradation of other specifications. For example, decreasing area may lead to decreased yield due to processing difficulties caused by the decreased area. As a result, a balancing of the various specifications is carried out to obtain acceptable devices. This is particularly so for process technologies in the sub-100 nm region.
- One example of a bitcell is known in the art as a 1R+1W bitcell design (where R stands for read and W stands for write). Such a bitcell is often used as a multi-port memory (for example, as a register file) bitcell in integrated circuit design. The IR section is known as the read channel section of the bitcell, and the 1W section is known as the storage cell section of the bitcell. The transistors may have different sizes, and due to the asymmetry in the transistors within the cell and the imposition of design rules such as discussed above, it is difficult to create an efficient, compact bitcell layout.
- The 1R+1W bitcell may have a 6T+2T configuration (6transistor+2transistor), with 6 transistors in the storage cell section and 2 transistors in the read channel section. A
generalized bitcell structure 10 is illustrated inFIG. 1 , in which the transistors in the storage cell section 12 are clustered together and then the transistors in theread channel section 14 are clustered together in an adjoining area to the side of the entire storage cell section 12. - Embodiments are described by way of example, with reference to the accompanying drawings, which are not drawn to scale, wherein:
-
FIG. 1 illustrates a generalized layout of a storage cell section and a read section of a bitcell; -
FIG. 2 illustrates an electrical schematic of a bitcell, in accordance with certain embodiments; -
FIG. 3 illustrates a top view layout of a bitcell having a storage cell section and a read section, in accordance with certain embodiments; -
FIG. 4 illustrates a top view layout of a bitcell including the relative position of the transistors within the storage cell section and the read section, in accordance with certain embodiments; -
FIG. 5 illustrates a top view of certain layers in a bitcell having a transistor layout similar to that illustrated inFIG. 4 , in accordance with certain embodiments; and -
FIG. 6 illustrates an electronic system arrangement in which embodiments may find application. -
FIG. 2 is a schematic of electrical connections for a bitcell such as a register file bitcell, having eight transistors. The schematic inFIG. 2 illustrates the electrical connections and not the actual physical layout (spacing, size, etc.) of the transistors. Such electrical connections may be used in certain embodiments described herein.FIG. 2 illustrates six transistors T1-T6 of the storage cell section, and two transistors T7-T8 of the read channel section. The transistors may be conventional field effect transistors including a'gate and source/drain regions. At the top ofFIG. 2 are the read word line (rdwl) and the write word line (wrwl). Coupled to the transistor T5 is the data in (di) line and coupled to transistor T6 is the data in bar (dib) line. Coupled to transistor T8 is the read out (ro) line. Nodes (n1 and n2), power (vcc), and ground (vss) lines are also shown. The 6T+2T organization can be readily observed. The 2T read channel section may use larger transistors than the 6T storage cell section, for good read performance. It should be noted that the storage cell transistors may also vary in size, according to standard memory cell design practice. - Certain embodiments described herein relate to an efficient, compact layout of a bitcell. Such a bitcell may in certain embodiments be used as a register file bitcell. The layout reconfigures the transistors away from the known organization of clustering the storage cell section and then appending the read channel section to the side of the entire storage cell section as in
FIG. 1 . Instead, the storage cell section extends around part of the read channel section to shorten signal paths and improve area efficiency. As a result, this cell is more compact and has an improved density. When this bitcell is arrayed out, a relatively regular and uniform pattern is obtained, which is advantageous for manufacturability. One example of such a bitcell layout is illustrated inFIG. 3 . -
FIG. 3 illustrates a topview bitcell layout 20 including the relative positions of the storage cell section and the read channel section. As seen inFIG. 3 , thestorage cell section 22 is wrapped around a portion of theread channel section 24, in order to shorten signal paths and improve area efficiency. This layout leads to superior density for memories utilizing such a 1R+1W bitcell. Thestorage cell section 22 as illustrated inFIG. 3 has a substantially L-shaped arrangement. The readchannel section 24 as illustrated inFIG. 3 has a substantially rectangular shape that fits into the open region defined by the L shape of the storage cell section. - Another way to describe the relative size of the
storage cell section 22 and reachchannel section 24 is that a dimension x2 of thestorage cell section 22 is greater than a dimension x1 of theread channel section 24, and a dimension y2 of thestorage cell section 22 is greater than a dimension y1 of theread channel section 24. -
FIG. 4 illustrates an example of an embodiment of abitcell 30 showing the relative locations of the transistors, with the transistors being positioned in astorage cell section 32 and theread channel section 34 similar to those illustrated inFIG. 3 . More specifically, as illustrated inFIG. 4 , two transistors, T3 and T2, are positioned in an upper portion of the L-shapedstorage cell section 32. Two transistors, T4 and T1, are positioned in a lower portion of the L-shapedstorage cell section 32. At least a portion of each of transistors T1 and T2 is positioned along a line (in a vertical direction as illustrated inFIG. 4 ), and at least a portion of each of transistors T1 and T4 is positioned along a line (in a horizontal direction as illustrated inFIG. 4 ). Likewise, at least a portion of each of transistors T4 and T3 is positioned along a line (in a vertical direction as illustrated inFIG. 4 ). The transistors T6 and T5 are positioned in a lower right hand portion of the L-shaped storage cell section. At least a portion of each of the transistors T6 and T5 is positioned along the same line (in a horizontal direction as illustrated inFIG. 4 ) as transistors T1 and T4. Readchannel region 34 includes transistors T7 and T8, with at least a portion of transistor T7 positioned along the same line (in a horizontal direction as illustrated inFIG. 4 ) as transistors T3 and T2. In addition, at least a portion of transistors T7 and T8 are positioned along a line (in a vertical direction as illustrated inFIG. 4 ) with transistor T6. In the embodiment illustrated inFIG. 4 , the lines described above as in a horizontal direction are orthogonal to the lines described above as in a vertical direction, the lines in the horizontal direction are parallel to each other, and the lines in the vertical direction are parallel to each other. In other embodiments, the transistors may be positioned along lines that intersect at angles other than orthogonal or parallel. - Certain embodiments may also include bitcells having more or less than 8 transistors, having a similar layout with a substantially L-shaped storage cell section and a read channel region that fits together with the storage cell section in a manner such as that shown in
FIG. 3 , for example. - In addition, certain embodiments, when viewed from above, may also be described as having a 2×2 array including transistors positioned in each of an upper left, upper right, lower left, and lower right portion of the 2×2 array. For example, the embodiment illustrated in
FIG. 4 includes at least part of transistors T7 and T8 in the upper right portion, transistors T3 and T2 in the upper left portion, transistors T4 and Ti in the lower left portion, and transistors T6 and T5 in the lower right portion of the 2×2 array. -
FIG. 5 illustrates a more detailed view of abitcell structure 100 having a transistor layout similar to that ofFIG. 4 , including various layers in the structure in accordance with one embodiment. For clarity, the view illustrated inFIG. 5 omits certain layers known to be included in transistor structures in known locations, including, but not necessarily limited to, gate oxide layer, oxide spacers, and interlayer dielectric.FIG. 5 also shows the relative location of the eight transistors as seen inFIG. 4 . The bitcell ofFIG. 5 has a 6T+2T structure with electrical connections such as those illustrated inFIG. 2 . - The
bitcell structure 100 includes asemiconductor substrate 102 having an n-well region 104 implanted therein. The substrate also includesdiffusion regions 105. The n-well region 104 is bounded by small dotted lines. Thediffusion regions 105 are bounded by alternating longer and shorter dashed lines, with sevendiffusion regions 105 illustrated inFIG. 5 .FIG. 5 illustrates four polysilicongate layer regions 106, bounded by alternating dotted and dashed lines. Nodes n1 and n2 are also shown. Firstmetal layer regions 108 and secondmetal layer regions 110 are also illustrated, with the firstmetal layer regions 108 bounded by dashed lines and the secondmetal layer regions 110 bounded by solid lines. The secondmetal layer regions 110 include power (vcc), ground (vss), read out (ro), data in (di), and data in bar (dib) lines. - A plurality of contact vias between various of the layers are also present in
FIG. 5 . Contact vias 112 are formed between thediffusion regions 105 in thesemiconductor substrate 102 and the firstmetal layer regions 108, or between thepolysilicon regions 106 and the firstmetal layer regions 108, with the contact vias 112 being bounded by short dashed lines. Contact vias 118 are formed between firstmetal layer regions 108 and secondmetal layer regions 110, with the contact vias 118 being bounded by short dashed lines. Contact vias 120 are formed between secondmetal layer regions 110 and third metal layer regions (not shown), with the contact vias 120 being bounded by solid lines. - The relative positions of the transistors T1-T8 are also illustrated in
FIG. 5 . The labels T1-T8 are positioned over the gate portion of the transistor. Transistors T3, T2, and T7 are positioned so that a line (in the horizontal direction as illustrated inFIG. 5 ) contacts at least part of each of these transistors. Similarly, transistors T4, T1, T6, and T5 are positioned so that a line (in the horizontal direction as illustrated inFIG. 5 ) contacts at least part of each of these transistors. It should also be noted that in certain embodiments, the transistors T5 and T6 may be slightly larger than the other storage cell transistors (T1-T4). - In addition, the transistors T3 and T4 are positioned so that a line (in the vertical direction as illustrated in
FIG. 5 ) contacts at least part of each of these transistors. The transistors T2 and T1 are also positioned so that a line (in the vertical direction as illustrated inFIG. 5 ) contacts at least part of each of these transistors. The transistors T7, T8, and T6 are also positioned so that a line (in the vertical direction as illustrated inFIG. 5 ) contacts at least part of each of these transistors. - Certain embodiments utilize arrays of bitcells having a structure such as that illustrated in
FIG. 5 , to form, for example, memory such as RAM (random access memory) that is used as a register file. When arrayed in a group of 8 rows and 8 columns of the bitcell structure ofFIG. 5 , for example, the bitcell pattern is relatively uniform and regular, which is advantageous for manufacturing and for predicting performance. - Certain embodiments using a bitcell layout as described above may include memories for a variety of chip designs including, but not limited to, processors, chipsets, ASIC's (application specific integrated circuits), and SOC's (system on a chip). Embodiments are applicable for advanced process technologies of the sub-100 nm region, including 90 nm and below.
- Embodiments may also relate to methods for forming a bitcell. A plurality of transistors in a storage cell section may be positioned in a substantially L-shaped arrangement, for example, the arrangement illustrated in
FIGS. 3-5 . A plurality of transistors in a read channel section are positioned within the region defined by the L-shape of the storage cell section, so that together the storage cell section and the read cell section are formed to have a substantially rectangular shape. -
FIG. 6 schematically illustrates one example of an electronic system environment in which aspects of described embodiments may be embodied. Other embodiments need not include all of the features specified inFIG. 6 , and may include alternative features not specified inFIG. 6 . - The
system 201 ofFIG. 6 may include at least one central processing unit (CPU) 203. TheCPU 203, also referred to as a microprocessor, may be attached to anintegrated circuit package 205, which is then coupled to a printedcircuit board 207, which in this embodiment, may be a motherboard. TheCPU 203 is an example of an electronic device that may include a plurality of bitcells (such as register file bitcells) having a structure in accordance with embodiments such as described above and illustrated inFIGS. 3-5 . - The
system 201 further may further includememory 209 and one ormore controllers motherboard 207. Themotherboard 207 may be a single layer or multi-layered board which has a plurality of conductive lines that provide communication between the circuits in thepackage 205 and other components mounted to theboard 207. Alternatively, one or more of theCPU 203,memory 209 andcontrollers CPU 203,memory 209 andcontrollers display 215 may also be included. - Any suitable operating system and various applications execute on the
CPU 203 and reside in thememory 209. The content residing inmemory 209 may be cached in accordance with known caching techniques. Programs and data inmemory 209 may be swapped intostorage 213 as part of memory management operations. Thesystem 201 may comprise any suitable computing device, including, but not limited to, a mainframe, server, personal computer, workstation, laptop, handheld computer, handheld gaming device, handheld entertainment device (for example, an MP3 (moving picture experts group layer-3 audio) player), PDA (personal digital assistant) telephony device (wireless or wired), network appliance, virtualization device, storage controller, network controller, etc. - The
controllers storage 213 in accordance with a storage protocol layer. The storage protocol of the layer may be any of a number of known storage protocols. Data being written to or read from thestorage 213 may be cached in accordance with known caching techniques. A network controller can include one or more protocol layers to send and receive network packets to and from remote devices over anetwork 217. Thenetwork 217 may comprise a Local Area Network (LAN), the Internet, a Wide Area Network (WAN), Storage Area Network (SAN), etc. Embodiments may be configured to transmit and receive data over a wireless network or connection. In certain embodiments, the network controller and various protocol layers may employ the Ethernet protocol over unshielded twisted pair cable, token ring protocol, Fibre Channel protocol, etc., or any other suitable network communication protocol. - While certain exemplary embodiments have been described above and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive, and that embodiments are not restricted to the specific constructions and arrangements shown and described since modifications may occur to those having ordinary skill in the art.
Claims (23)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/241,390 US7196923B1 (en) | 2005-09-30 | 2005-09-30 | Bitcell layout |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/241,390 US7196923B1 (en) | 2005-09-30 | 2005-09-30 | Bitcell layout |
Publications (2)
Publication Number | Publication Date |
---|---|
US7196923B1 US7196923B1 (en) | 2007-03-27 |
US20070076461A1 true US20070076461A1 (en) | 2007-04-05 |
Family
ID=37886106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/241,390 Expired - Fee Related US7196923B1 (en) | 2005-09-30 | 2005-09-30 | Bitcell layout |
Country Status (1)
Country | Link |
---|---|
US (1) | US7196923B1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090001440A1 (en) * | 2007-06-26 | 2009-01-01 | Max Wei | Semiconductor device with buried source rail |
WO2012012538A2 (en) | 2010-07-20 | 2012-01-26 | University Of Virginia Patent Foundation | Memory cell |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5698873A (en) * | 1996-03-08 | 1997-12-16 | Lsi Logic Corporation | High density gate array base cell architecture |
US5818751A (en) * | 1997-06-21 | 1998-10-06 | Industrial Technology Research Institute | Single-port SRAM with no read/write collisions |
US6734573B2 (en) * | 2002-07-09 | 2004-05-11 | Renesas Technology Corp. | Semiconductor memory having access transistors formed in a single well and driver transistors formed in wells different from the single well |
US6898111B2 (en) * | 2001-06-28 | 2005-05-24 | Matsushita Electric Industrial Co., Ltd. | SRAM device |
US6985379B2 (en) * | 2002-04-01 | 2006-01-10 | Renesas Technology Corp. | Semiconductor memory device |
US20060067108A1 (en) * | 2004-09-25 | 2006-03-30 | Rabiul Islam | Bitcell having a unity beta ratio |
US20060072356A1 (en) * | 2004-09-24 | 2006-04-06 | Intel Corporation | State-retentive mixed register file array |
-
2005
- 2005-09-30 US US11/241,390 patent/US7196923B1/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5698873A (en) * | 1996-03-08 | 1997-12-16 | Lsi Logic Corporation | High density gate array base cell architecture |
US5818751A (en) * | 1997-06-21 | 1998-10-06 | Industrial Technology Research Institute | Single-port SRAM with no read/write collisions |
US6898111B2 (en) * | 2001-06-28 | 2005-05-24 | Matsushita Electric Industrial Co., Ltd. | SRAM device |
US6985379B2 (en) * | 2002-04-01 | 2006-01-10 | Renesas Technology Corp. | Semiconductor memory device |
US6734573B2 (en) * | 2002-07-09 | 2004-05-11 | Renesas Technology Corp. | Semiconductor memory having access transistors formed in a single well and driver transistors formed in wells different from the single well |
US20060072356A1 (en) * | 2004-09-24 | 2006-04-06 | Intel Corporation | State-retentive mixed register file array |
US20060067108A1 (en) * | 2004-09-25 | 2006-03-30 | Rabiul Islam | Bitcell having a unity beta ratio |
Also Published As
Publication number | Publication date |
---|---|
US7196923B1 (en) | 2007-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6599880B2 (en) | Device comprising a memory array having a source contact adjacent to an edge of the source | |
US20190088585A1 (en) | Memory Circuits and Routing of Conductive Layers Thereof | |
CN105144381B (en) | Three-dimensional (3D) memory cell with the read/write port on the different layers of integrated circuit and access logic unit | |
US7269056B1 (en) | Power grid design for split-word line style memory cell | |
US7760578B2 (en) | Enhanced power distribution in an integrated circuit | |
JP2008182246A (en) | Structure of integrated circuit module that reduces handling damage | |
US20160056161A1 (en) | Memory device | |
US20200328216A1 (en) | Semiconductor structure | |
US7196923B1 (en) | Bitcell layout | |
US20240032270A1 (en) | Cross fet sram cell layout | |
US9881992B2 (en) | Semiconductor integrated circuit device having with a reservoir capacitor | |
US20180182722A1 (en) | Semiconductor memory device including a dummy word line | |
US8759914B1 (en) | Deep sub-micron interconnection circuitry with shielded layer structure | |
KR20120121727A (en) | Semiconductor cell and method for forming the same, cell array, semiconductor device, semiconductor module, semiconductor system, electronic unit and electronic system | |
US9997223B2 (en) | Semiconductor device including metal-oxide-semiconductor disposed in a column decoder region | |
US20220068778A1 (en) | Apparatuses and systems having ball grid arrays and associated microelectronic devices and device packages | |
JP6466305B2 (en) | Electrical interconnect for electronic packages | |
WO2021104411A1 (en) | Integrated circuit and electronic apparatus | |
US10020295B2 (en) | Semiconductor device comprising a plurality of drivers formed in different active regions having all source regions, drain regions of a plurality of MOSFETs connected together | |
KR20090051507A (en) | Semiconductor device having sense amplifiers and electronic system employing the same | |
CN114815490B (en) | Mask layout, memory cell structure and memory | |
WO2023097662A1 (en) | Memory and electronic device | |
US9978428B2 (en) | Semiconductor device and power distribution network | |
US9793210B2 (en) | Power line layout structure of semiconductor device and method for forming the same | |
US9955605B2 (en) | Hardware interface with space-efficient cell pattern |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HONG, JOSEPH;ISLAM, RABIUL;ANNOJVALA, SUBODH;AND OTHERS;REEL/FRAME:017402/0365;SIGNING DATES FROM 20051215 TO 20051216 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20190327 |