US20040047176A1 - Static random access memory with symmetric leakage-compensated bit line - Google Patents
Static random access memory with symmetric leakage-compensated bit line Download PDFInfo
- Publication number
- US20040047176A1 US20040047176A1 US10/241,791 US24179102A US2004047176A1 US 20040047176 A1 US20040047176 A1 US 20040047176A1 US 24179102 A US24179102 A US 24179102A US 2004047176 A1 US2004047176 A1 US 2004047176A1
- Authority
- US
- United States
- Prior art keywords
- source
- drain terminal
- bit line
- terminal connected
- nmosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Definitions
- Embodiments of the present invention relate to circuits, and more particularly, to static random access memory circuits.
- SRAM Static Random Access Memory
- CPU static Random Access Memory
- Cache 104 may be part of a memory hierarchy to store instructions and data; where system memory 108 is part of the memory hierarchy.
- Communication between microprocessor 102 with memory 108 is facilitated by memory controller (or chipset) 110 , which also facilitates in communicating with peripheral components 112 .
- Microprocessor communicates directly with memory controller 110 via bus or point-to-point interconnect 114 .
- subthreshold leakage current in transistors may present problems. For example, reading a memory cell in SRAM usually relies upon the development of a differential voltage on a pair of bit lines, where the differential voltage is indicative of the stored information bit. There are many other memory cells sharing the same pair of bit lines. During a read operation, the subthreshold leakage current in the cells not being read may cause an incorrect differential voltage to be sensed on the bit lines.
- Memory cell 202 comprising cross-coupled inverters 204 and 206 is being read by asserting word line 208 HIGH (e.g., V CC ).
- Memory cell 202 provides a differential voltage on bit lines 210 and 212 .
- bit lines 210 and 212 For simplicity, only two other memory cells, illustrated in dashed lines, are shown sharing bit lines 210 and 212 , but in practice there will be many more such memory cells. (Assume in the discussion that follows regarding FIG. 2 that all other memory cells sharing the bit lines have the same states as those shown in dashed lines.)
- Memory cell 202 has a state in which node 214 is LOW (e.g., V SS ) and node 216 is HIGH.
- a worst case scenario is illustrated in which those memory cells not being read are such that they store data bits in which nodes 214 a and 214 b are HIGH and nodes 216 a and 216 b are LOW.
- word line 208 asserted HIGH
- access nMOSFETs n-Metal Oxide Semiconductor Field Effect Transistor
- bit line 210 With both bit lines pre-charged HIGH, bit line 210 will ideally discharge and bit line 212 will ideally maintain its HIGH state so that sense amplifier 222 will sense the correct differential voltage.
- access nMOSFETs 218 a , 218 b , 220 a , and 220 b are OFF, there will be leakage current through them. This leakage current works against memory cell 202 discharging bit line 210 , and works against memory cell 202 keeping bit line 212 HIGH. As a result, a read operation is more susceptible to noise on the bit lines causing sense amplifier 222 to provide an incorrect result.
- FIG. 1 illustrates at a high level a portion of a prior art computer system.
- FIG. 2 illustrates a prior art SRAM.
- FIG. 3 illustrates a memory cell in a SRAM according to an embodiment of the present invention.
- FIG. 4 illustrates memory cell layout according to an embodiment of the present invention.
- FIG. 3 shows memory cell 302 connected to bit lines 304 and 306 , and accessed by word line 308 .
- write ports are not shown, and only one memory cell is illustrated, but in practice many memory cells share bit lines 304 and 306 .
- the information state is stored by cross-coupled inverters 310 and 312 , and the stored information state is access by asserting word line 308 HIGH so that access nMOSFETs 324 and 326 switch ON.
- nMOSFET 314 is coupled with one of its source/drain terminals connected to node 318 of cross-coupled inverters 310 and 312 , and its other source/drain terminal is connected to bit line 304 .
- nMOSFET 316 is coupled with one of its source/drain terminals connected to node 320 of cross-coupled inverters 310 and 312 , and its other source/drain terminal is connected to bit line 306 .
- the gates of both nMOSFETs 314 and 316 are connected to ground 322 (V SS ).
- nMOSFETs 314 and 316 With the gates of nMOSFETs 314 and 316 connected to ground 322 , these nMOSFETs are OFF, but subthreshold leakage current will be conducted. Subthreshold leakage current through nMOSFETs 314 and 316 are denoted respectively in FIG. 3 by i 3 and i 4 as shown. Consider the case in which memory cell 302 is not being read, so that word line 308 is LOW and access nMOSFETs 324 and 326 are OFF. Subthreshold leakage current will be conducted through nMOSFETs 324 and 326 , which are respectively denoted by i 1 and i 2 as shown in FIG. 3.
- bit lines 304 and 306 are identical in structure to that of memory cell 302 .
- the bit lines are pre-charged to V CC , so that the above expressions for the subthreshold leakage currents hold for all memory cells not being read. Note that as a read operation progresses, the memory cell being read causes a differential voltage to develop on the bit lines, and thus the various sub-threshold leakage currents are only approximately balanced. But as the differential voltage develops, the sense amplifier connected to the bit lines will eventually evaluate, so that this approximation becomes less of an issue.
- the differential voltage developed between a common pair of bit lines is highly insensitive to the number of memory cells sharing the bit lines, so that memory organization is simplified.
- the memory cell of FIG. 3 may take advantage of low threshold voltage nMOSFETs as well as relatively high leaky nMOSFETs so as to speed up the differential voltage development. Consequently, it is expected that high performance SRAMs may be realized by utilizing the memory cell of FIG. 3.
- memory cells of the kind illustrated in FIG. 3 may be organized in which adjacent memory cells share a bit line.
- the word lines are connected to the memory cells so that no two memory cells sharing the same bit line are accessed during the same read operation.
- FIG. 4 Such a memory organization is indicated in FIG. 4 , where for simplicity only two memory cells are explicitly shown. In practice, a large number of memory cells would be laid out in the “x” (word line) direction and “y” (bit line) direction.
- memory cell 402 has its access nMOSFETs connected to word line 404 , and is connected to bit lines 406 and 408 .
- memory cell 410 has its access nMOSFETs connected to word line 402 , which is adjacent to word line 404 , and is connected to bit lines 408 and 412 .
- bit line 408 is shared by both memory cells 402 and 410 . In this way, the word line direction (x direction) of the memory cells may be reduced, so that die area is more efficiently used.
Abstract
Description
- Embodiments of the present invention relate to circuits, and more particularly, to static random access memory circuits.
- SRAM (Static Random Access Memory) is a memory technology that finds important applications in high speed caches or register files. Such high speed memory is often integrated on a die with a microprocessor core, and may be used to store instructions, as well as data used and generated by a microprocessor. For example, a portion of a computer system is abstracted at a high level in FIG. 1.
Microprocessor 102 comprisescache 104 andregister files 106, which in turn comprises SRAM memory.Cache 104 may be part of a memory hierarchy to store instructions and data; wheresystem memory 108 is part of the memory hierarchy. Communication betweenmicroprocessor 102 withmemory 108 is facilitated by memory controller (or chipset) 110, which also facilitates in communicating withperipheral components 112. Microprocessor communicates directly withmemory controller 110 via bus or point-to-point interconnect 114. - As process technology scales to smaller and smaller dimensions, subthreshold leakage current in transistors may present problems. For example, reading a memory cell in SRAM usually relies upon the development of a differential voltage on a pair of bit lines, where the differential voltage is indicative of the stored information bit. There are many other memory cells sharing the same pair of bit lines. During a read operation, the subthreshold leakage current in the cells not being read may cause an incorrect differential voltage to be sensed on the bit lines.
- The above example is illustrated in FIG. 2.
Memory cell 202 comprisingcross-coupled inverters word line 208 HIGH (e.g., VCC).Memory cell 202 provides a differential voltage onbit lines bit lines Memory cell 202 has a state in whichnode 214 is LOW (e.g., VSS) andnode 216 is HIGH. A worst case scenario is illustrated in which those memory cells not being read are such that they store data bits in whichnodes nodes 216 a and 216 b are LOW. Withword line 208 asserted HIGH, access nMOSFETs (n-Metal Oxide Semiconductor Field Effect Transistor) 218 and 220 are ON. With both bit lines pre-charged HIGH,bit line 210 will ideally discharge andbit line 212 will ideally maintain its HIGH state so thatsense amplifier 222 will sense the correct differential voltage. However, although access nMOSFETs 218 a, 218 b, 220 a, and 220 b are OFF, there will be leakage current through them. This leakage current works againstmemory cell 202discharging bit line 210, and works againstmemory cell 202 keepingbit line 212 HIGH. As a result, a read operation is more susceptible to noise on the bit lines causingsense amplifier 222 to provide an incorrect result. - FIG. 1 illustrates at a high level a portion of a prior art computer system.
- FIG. 2 illustrates a prior art SRAM.
- FIG. 3 illustrates a memory cell in a SRAM according to an embodiment of the present invention.
- FIG. 4 illustrates memory cell layout according to an embodiment of the present invention.
- FIG. 3 shows
memory cell 302 connected tobit lines word line 308. For simplicity, write ports are not shown, and only one memory cell is illustrated, but in practice many memory cells sharebit lines cross-coupled inverters word line 308 HIGH so that access nMOSFETs 324 and 326 switch ON. nMOSFET 314 is coupled with one of its source/drain terminals connected tonode 318 ofcross-coupled inverters bit line 304. nMOSFET 316 is coupled with one of its source/drain terminals connected tonode 320 ofcross-coupled inverters bit line 306. The gates of both nMOSFETs 314 and 316 are connected to ground 322 (VSS). - With the gates of
nMOSFETs ground 322, these nMOSFETs are OFF, but subthreshold leakage current will be conducted. Subthreshold leakage current throughnMOSFETs memory cell 302 is not being read, so thatword line 308 is LOW and accessnMOSFETs nMOSFETs bit lines nMOSFET nMOSFETs memory cell 302 does not contribute to a differential voltage onbit lines - Although not shown, other memory cells sharing
bit lines memory cell 302. Before a memory cell is read, the bit lines are pre-charged to VCC, so that the above expressions for the subthreshold leakage currents hold for all memory cells not being read. Note that as a read operation progresses, the memory cell being read causes a differential voltage to develop on the bit lines, and thus the various sub-threshold leakage currents are only approximately balanced. But as the differential voltage develops, the sense amplifier connected to the bit lines will eventually evaluate, so that this approximation becomes less of an issue. Consequently, the differential voltage developed between a common pair of bit lines is highly insensitive to the number of memory cells sharing the bit lines, so that memory organization is simplified. Furthermore, because of the balanced subthreshold leakage currents, the memory cell of FIG. 3 may take advantage of low threshold voltage nMOSFETs as well as relatively high leaky nMOSFETs so as to speed up the differential voltage development. Consequently, it is expected that high performance SRAMs may be realized by utilizing the memory cell of FIG. 3. - In one particular embodiment, memory cells of the kind illustrated in FIG. 3 may be organized in which adjacent memory cells share a bit line. The word lines are connected to the memory cells so that no two memory cells sharing the same bit line are accessed during the same read operation. Such a memory organization is indicated in FIG.4, where for simplicity only two memory cells are explicitly shown. In practice, a large number of memory cells would be laid out in the “x” (word line) direction and “y” (bit line) direction. As seen in FIG. 4,
memory cell 402 has its access nMOSFETs connected toword line 404, and is connected tobit lines memory cell 402 in the word line direction,memory cell 410, has its access nMOSFETs connected toword line 402, which is adjacent toword line 404, and is connected tobit lines bit line 408 is shared by bothmemory cells - Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below.
Claims (9)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/241,791 US6707708B1 (en) | 2002-09-10 | 2002-09-10 | Static random access memory with symmetric leakage-compensated bit line |
TW092122741A TWI232579B (en) | 2002-09-10 | 2003-08-19 | Static random access memory with symmetric leakage-compensated bit line |
AU2003273284A AU2003273284A1 (en) | 2002-09-10 | 2003-09-05 | Static random access memory with symmetric leakage-compensated bit line |
PCT/US2003/027789 WO2004025661A2 (en) | 2002-09-10 | 2003-09-05 | Static random access memory with symmetric leakage-compensated bit line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/241,791 US6707708B1 (en) | 2002-09-10 | 2002-09-10 | Static random access memory with symmetric leakage-compensated bit line |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040047176A1 true US20040047176A1 (en) | 2004-03-11 |
US6707708B1 US6707708B1 (en) | 2004-03-16 |
Family
ID=31946378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/241,791 Expired - Fee Related US6707708B1 (en) | 2002-09-10 | 2002-09-10 | Static random access memory with symmetric leakage-compensated bit line |
Country Status (4)
Country | Link |
---|---|
US (1) | US6707708B1 (en) |
AU (1) | AU2003273284A1 (en) |
TW (1) | TWI232579B (en) |
WO (1) | WO2004025661A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1624460A2 (en) * | 2004-08-04 | 2006-02-08 | Stmicroelectronics SA | SRAM type memory element, memory comprising such a memory element, associated reading method and writing method |
US20090185409A1 (en) * | 2008-01-22 | 2009-07-23 | International Business Machines Corporation | Enhanced static random access memory stability using asymmetric access transistors and design structure for same |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6801463B2 (en) * | 2002-10-17 | 2004-10-05 | Intel Corporation | Method and apparatus for leakage compensation with full Vcc pre-charge |
US7092279B1 (en) * | 2003-03-24 | 2006-08-15 | Sheppard Douglas P | Shared bit line memory device and method |
US6967875B2 (en) * | 2003-04-21 | 2005-11-22 | United Microelectronics Corp. | Static random access memory system with compensating-circuit for bitline leakage |
US7123500B2 (en) * | 2003-12-30 | 2006-10-17 | Intel Corporation | 1P1N 2T gain cell |
US7224205B2 (en) * | 2004-07-07 | 2007-05-29 | Semi Solutions, Llc | Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors |
US8247840B2 (en) * | 2004-07-07 | 2012-08-21 | Semi Solutions, Llc | Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode |
US7683433B2 (en) * | 2004-07-07 | 2010-03-23 | Semi Solution, Llc | Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors |
US7375402B2 (en) * | 2004-07-07 | 2008-05-20 | Semi Solutions, Llc | Method and apparatus for increasing stability of MOS memory cells |
US7651905B2 (en) * | 2005-01-12 | 2010-01-26 | Semi Solutions, Llc | Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts |
US7898297B2 (en) * | 2005-01-04 | 2011-03-01 | Semi Solution, Llc | Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits |
US7212040B2 (en) * | 2005-05-16 | 2007-05-01 | Intelliserv, Inc. | Stabilization of state-holding circuits at high temperatures |
US7863689B2 (en) * | 2006-09-19 | 2011-01-04 | Semi Solutions, Llc. | Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor |
US8006164B2 (en) | 2006-09-29 | 2011-08-23 | Intel Corporation | Memory cell supply voltage control based on error detection |
US7812631B2 (en) * | 2006-12-12 | 2010-10-12 | Intel Corporation | Sleep transistor array apparatus and method with leakage control circuitry |
US7408800B1 (en) * | 2007-05-03 | 2008-08-05 | International Business Machines Corporation | Apparatus and method for improved SRAM device performance through double gate topology |
US20080273366A1 (en) * | 2007-05-03 | 2008-11-06 | International Business Machines Corporation | Design structure for improved sram device performance through double gate topology |
JP2009064482A (en) * | 2007-09-04 | 2009-03-26 | Nec Electronics Corp | Semiconductor memory device |
US8207784B2 (en) * | 2008-02-12 | 2012-06-26 | Semi Solutions, Llc | Method and apparatus for MOSFET drain-source leakage reduction |
TWI514379B (en) * | 2014-07-14 | 2015-12-21 | Winbond Electronics Corp | Memory device for reducing leakage current |
US10229738B2 (en) | 2017-04-25 | 2019-03-12 | International Business Machines Corporation | SRAM bitline equalization using phase change material |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4914629A (en) * | 1988-09-07 | 1990-04-03 | Texas Instruments, Incorporated | Memory cell including single event upset rate reduction circuitry |
US5426614A (en) * | 1994-01-13 | 1995-06-20 | Texas Instruments Incorporated | Memory cell with programmable antifuse technology |
US6262911B1 (en) * | 2000-06-22 | 2001-07-17 | International Business Machines Corporation | Method to statically balance SOI parasitic effects, and eight device SRAM cells using same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11260063A (en) * | 1998-03-10 | 1999-09-24 | Hitachi Ltd | Semiconductor device |
JP4073691B2 (en) * | 2002-03-19 | 2008-04-09 | 株式会社ルネサステクノロジ | Semiconductor memory device |
-
2002
- 2002-09-10 US US10/241,791 patent/US6707708B1/en not_active Expired - Fee Related
-
2003
- 2003-08-19 TW TW092122741A patent/TWI232579B/en not_active IP Right Cessation
- 2003-09-05 AU AU2003273284A patent/AU2003273284A1/en not_active Abandoned
- 2003-09-05 WO PCT/US2003/027789 patent/WO2004025661A2/en not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4914629A (en) * | 1988-09-07 | 1990-04-03 | Texas Instruments, Incorporated | Memory cell including single event upset rate reduction circuitry |
US5426614A (en) * | 1994-01-13 | 1995-06-20 | Texas Instruments Incorporated | Memory cell with programmable antifuse technology |
US6262911B1 (en) * | 2000-06-22 | 2001-07-17 | International Business Machines Corporation | Method to statically balance SOI parasitic effects, and eight device SRAM cells using same |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1624460A2 (en) * | 2004-08-04 | 2006-02-08 | Stmicroelectronics SA | SRAM type memory element, memory comprising such a memory element, associated reading method and writing method |
FR2874117A1 (en) * | 2004-08-04 | 2006-02-10 | St Microelectronics Sa | MEMORY POINT OF SRAM TYPE, MEMORY COMPRISING SUCH A MEMORY POINT, READING METHOD AND ASSOCIATED WRITING METHOD |
EP1624460A3 (en) * | 2004-08-04 | 2006-07-26 | Stmicroelectronics SA | SRAM type memory element, memory comprising such a memory element, associated reading method and writing method |
US20060291273A1 (en) * | 2004-08-04 | 2006-12-28 | Stmicroelectronics Sa | Sram memory cell and associated read and write method |
US7280387B2 (en) | 2004-08-04 | 2007-10-09 | Stmicroelectronics Sa | SRAM cell comprising a reference transistor for neutralizing leakage current and associated read and write method |
US20090185409A1 (en) * | 2008-01-22 | 2009-07-23 | International Business Machines Corporation | Enhanced static random access memory stability using asymmetric access transistors and design structure for same |
US8139400B2 (en) | 2008-01-22 | 2012-03-20 | International Business Machines Corporation | Enhanced static random access memory stability using asymmetric access transistors and design structure for same |
US8526219B2 (en) | 2008-01-22 | 2013-09-03 | International Business Machines Corporation | Enhanced static random access memory stability using asymmetric access transistors and design structure for same |
Also Published As
Publication number | Publication date |
---|---|
AU2003273284A1 (en) | 2004-04-30 |
WO2004025661A3 (en) | 2004-12-09 |
US6707708B1 (en) | 2004-03-16 |
TW200410398A (en) | 2004-06-16 |
TWI232579B (en) | 2005-05-11 |
WO2004025661A2 (en) | 2004-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6707708B1 (en) | Static random access memory with symmetric leakage-compensated bit line | |
US5831896A (en) | Memory cell | |
US5040146A (en) | Static memory cell | |
US10090042B2 (en) | Memory with keeper circuit | |
US6650589B2 (en) | Low voltage operation of static random access memory | |
KR101293528B1 (en) | Low leakage high performance static random access memory cell using dual-technology transistors | |
US7613032B2 (en) | Semiconductor memory device and control method thereof | |
US7123504B2 (en) | Semiconductor integrated circuit device having static random access memory mounted thereon | |
JP2006196124A (en) | Memory cell and semiconductor integrated circuit device | |
US7161827B2 (en) | SRAM having improved cell stability and method therefor | |
US7525867B2 (en) | Storage circuit and method therefor | |
US20060018147A1 (en) | Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells | |
US6493256B1 (en) | Semiconductor memory device | |
US6504788B1 (en) | Semiconductor memory with improved soft error resistance | |
US7423899B2 (en) | SRAM device having forward body bias control | |
US7142465B2 (en) | Semiconductor memory | |
US6909652B2 (en) | SRAM bit-line reduction | |
US9607669B2 (en) | Semiconductor memory device including precharge circuit | |
KR0158113B1 (en) | Bit line precharge circuit and equalizing circuit | |
CN116599013A (en) | ESD protection circuit and method for virtual memory cell in SRAM | |
KR20020088223A (en) | Circuit for Controlling Power Voltage of Static Random Access Memory | |
KR20000032732A (en) | 2-port sram circuit | |
KR980011416A (en) | Memory cell data sensing circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ALVANDPOUR, ATILA;SOMASEKHAR, DINESH;HSU, STEVEN K.;AND OTHERS;REEL/FRAME:013499/0983;SIGNING DATES FROM 20021030 TO 20021031 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20160316 |