DE69809450D1 - Datenverarbeitungsvorrichtung - Google Patents
DatenverarbeitungsvorrichtungInfo
- Publication number
- DE69809450D1 DE69809450D1 DE69809450T DE69809450T DE69809450D1 DE 69809450 D1 DE69809450 D1 DE 69809450D1 DE 69809450 T DE69809450 T DE 69809450T DE 69809450 T DE69809450 T DE 69809450T DE 69809450 D1 DE69809450 D1 DE 69809450D1
- Authority
- DE
- Germany
- Prior art keywords
- computing device
- computing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/928,444 US6085315A (en) | 1997-09-12 | 1997-09-12 | Data processing device with loop pipeline |
| PCT/US1998/018673 WO1999014664A1 (en) | 1997-09-12 | 1998-09-04 | Data processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69809450D1 true DE69809450D1 (de) | 2002-12-19 |
| DE69809450T2 DE69809450T2 (de) | 2003-07-03 |
Family
ID=25456239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69809450T Expired - Lifetime DE69809450T2 (de) | 1997-09-12 | 1998-09-04 | Datenverarbeitungsvorrichtung |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6085315A (de) |
| EP (1) | EP1012705B1 (de) |
| JP (1) | JP2001517819A (de) |
| KR (1) | KR20010030587A (de) |
| DE (1) | DE69809450T2 (de) |
| IL (1) | IL134459A0 (de) |
| WO (1) | WO1999014664A1 (de) |
Families Citing this family (95)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002532775A (ja) * | 1998-12-08 | 2002-10-02 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | インタープリタプログラム実行方法 |
| EP1163577B1 (de) * | 1999-03-17 | 2003-11-26 | Infineon Technologies AG | Cachen kurzer programmschleifen innerhalb eines instruktions-fifos |
| EP1039375A1 (de) * | 1999-03-19 | 2000-09-27 | Motorola, Inc. | Verfahren und Vorrichtung zur Durchführung von Schleifen mit kleinem Verwaltungsaufwand |
| US6393551B1 (en) * | 1999-05-26 | 2002-05-21 | Infineon Technologies North America Corp. | Reducing instruction transactions in a microprocessor |
| US6598155B1 (en) * | 2000-01-31 | 2003-07-22 | Intel Corporation | Method and apparatus for loop buffering digital signal processing instructions |
| US6963965B1 (en) * | 1999-11-30 | 2005-11-08 | Texas Instruments Incorporated | Instruction-programmable processor with instruction loop cache |
| US7302557B1 (en) | 1999-12-27 | 2007-11-27 | Impact Technologies, Inc. | Method and apparatus for modulo scheduled loop execution in a processor architecture |
| US6732203B2 (en) * | 2000-01-31 | 2004-05-04 | Intel Corporation | Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus |
| US6918028B1 (en) * | 2000-03-28 | 2005-07-12 | Analog Devices, Inc. | Pipelined processor including a loosely coupled side pipe |
| US6757817B1 (en) * | 2000-05-19 | 2004-06-29 | Intel Corporation | Apparatus having a cache and a loop buffer |
| US7065636B2 (en) * | 2000-12-20 | 2006-06-20 | Intel Corporation | Hardware loops and pipeline system using advanced generation of loop parameters |
| US6842895B2 (en) * | 2000-12-21 | 2005-01-11 | Freescale Semiconductor, Inc. | Single instruction for multiple loops |
| TW567695B (en) * | 2001-01-17 | 2003-12-21 | Ibm | Digital baseband system |
| JP2002229779A (ja) * | 2001-02-02 | 2002-08-16 | Mitsubishi Electric Corp | 情報処理装置 |
| US6950929B2 (en) * | 2001-05-24 | 2005-09-27 | Samsung Electronics Co., Ltd. | Loop instruction processing using loop buffer in a data processing device having a coprocessor |
| US7249248B2 (en) * | 2002-11-25 | 2007-07-24 | Intel Corporation | Method, apparatus, and system for variable increment multi-index looping operations |
| US7159103B2 (en) * | 2003-03-24 | 2007-01-02 | Infineon Technologies Ag | Zero-overhead loop operation in microprocessor having instruction buffer |
| DE102005001679B4 (de) * | 2005-01-13 | 2008-11-13 | Infineon Technologies Ag | Mikroprozessor-Einrichtung, und Verfahren zur Branch-Prediktion für conditional Branch-Befehle in einer Mikroprozessor-Einrichtung |
| US7711934B2 (en) * | 2005-10-31 | 2010-05-04 | Mips Technologies, Inc. | Processor core and method for managing branch misprediction in an out-of-order processor pipeline |
| US7734901B2 (en) * | 2005-10-31 | 2010-06-08 | Mips Technologies, Inc. | Processor core and method for managing program counter redirection in an out-of-order processor pipeline |
| US7873820B2 (en) * | 2005-11-15 | 2011-01-18 | Mips Technologies, Inc. | Processor utilizing a loop buffer to reduce power consumption |
| US7562191B2 (en) * | 2005-11-15 | 2009-07-14 | Mips Technologies, Inc. | Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme |
| US7496771B2 (en) * | 2005-11-15 | 2009-02-24 | Mips Technologies, Inc. | Processor accessing a scratch pad on-demand to reduce power consumption |
| US7721071B2 (en) * | 2006-02-28 | 2010-05-18 | Mips Technologies, Inc. | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor |
| US20070204139A1 (en) | 2006-02-28 | 2007-08-30 | Mips Technologies, Inc. | Compact linked-list-based multi-threaded instruction graduation buffer |
| EP2477109B1 (de) | 2006-04-12 | 2016-07-13 | Soft Machines, Inc. | Vorrichtung und Verfahren zur Verarbeitung einer Anweisungsmatrix zur Spezifizierung von parallelen und abhängigen Betriebsabläufen |
| US7370178B1 (en) * | 2006-07-14 | 2008-05-06 | Mips Technologies, Inc. | Method for latest producer tracking in an out-of-order processor, and applications thereof |
| US20080016326A1 (en) * | 2006-07-14 | 2008-01-17 | Mips Technologies, Inc. | Latest producer tracking in an out-of-order processor, and applications thereof |
| US7657708B2 (en) * | 2006-08-18 | 2010-02-02 | Mips Technologies, Inc. | Methods for reducing data cache access power in a processor using way selection bits |
| US7650465B2 (en) | 2006-08-18 | 2010-01-19 | Mips Technologies, Inc. | Micro tag array having way selection bits for reducing data cache access power |
| US7647475B2 (en) * | 2006-09-06 | 2010-01-12 | Mips Technologies, Inc. | System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue |
| US8032734B2 (en) * | 2006-09-06 | 2011-10-04 | Mips Technologies, Inc. | Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor |
| US7594079B2 (en) | 2006-09-29 | 2009-09-22 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
| US8078846B2 (en) | 2006-09-29 | 2011-12-13 | Mips Technologies, Inc. | Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated |
| US20080082793A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Detection and prevention of write-after-write hazards, and applications thereof |
| US9946547B2 (en) * | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
| EP2523101B1 (de) | 2006-11-14 | 2014-06-04 | Soft Machines, Inc. | Vorrichtung und Verfahren zum Verarbeiten von komplexen Anweisungsformaten in einer Multi-Thread-Architektur, die verschiedene Kontextschaltungsmodi und Visualisierungsschemen unterstützt |
| US7987347B2 (en) * | 2006-12-22 | 2011-07-26 | Broadcom Corporation | System and method for implementing a zero overhead loop |
| US7991985B2 (en) * | 2006-12-22 | 2011-08-02 | Broadcom Corporation | System and method for implementing and utilizing a zero overhead loop |
| KR100861073B1 (ko) * | 2007-01-23 | 2008-10-01 | 충북대학교 산학협력단 | 적응형 파이프라인을 적용한 병렬 처리 프로세서 구조 |
| DE602007005790D1 (de) * | 2007-06-26 | 2010-05-20 | Ericsson Telefon Ab L M | Datenverarbeitungseinheit für Anweisungen in geschachtelten Schleifen |
| US20090109996A1 (en) * | 2007-10-29 | 2009-04-30 | Hoover Russell D | Network on Chip |
| US20090125706A1 (en) * | 2007-11-08 | 2009-05-14 | Hoover Russell D | Software Pipelining on a Network on Chip |
| US20090125703A1 (en) * | 2007-11-09 | 2009-05-14 | Mejdrich Eric O | Context Switching on a Network On Chip |
| US8261025B2 (en) | 2007-11-12 | 2012-09-04 | International Business Machines Corporation | Software pipelining on a network on chip |
| US8526422B2 (en) * | 2007-11-27 | 2013-09-03 | International Business Machines Corporation | Network on chip with partitions |
| US7917703B2 (en) * | 2007-12-13 | 2011-03-29 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidate commands |
| US8473667B2 (en) * | 2008-01-11 | 2013-06-25 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidation messages |
| US8010750B2 (en) * | 2008-01-17 | 2011-08-30 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidate commands |
| US8018466B2 (en) * | 2008-02-12 | 2011-09-13 | International Business Machines Corporation | Graphics rendering on a network on chip |
| US7913010B2 (en) * | 2008-02-15 | 2011-03-22 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
| US8490110B2 (en) * | 2008-02-15 | 2013-07-16 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
| US20090245257A1 (en) * | 2008-04-01 | 2009-10-01 | International Business Machines Corporation | Network On Chip |
| US20090260013A1 (en) * | 2008-04-14 | 2009-10-15 | International Business Machines Corporation | Computer Processors With Plural, Pipelined Hardware Threads Of Execution |
| US20090271172A1 (en) * | 2008-04-24 | 2009-10-29 | International Business Machines Corporation | Emulating A Computer Run Time Environment |
| US8078850B2 (en) * | 2008-04-24 | 2011-12-13 | International Business Machines Corporation | Branch prediction technique using instruction for resetting result table pointer |
| US8423715B2 (en) | 2008-05-01 | 2013-04-16 | International Business Machines Corporation | Memory management among levels of cache in a memory hierarchy |
| US7991978B2 (en) * | 2008-05-09 | 2011-08-02 | International Business Machines Corporation | Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor |
| US7861065B2 (en) * | 2008-05-09 | 2010-12-28 | International Business Machines Corporation | Preferential dispatching of computer program instructions |
| US7958340B2 (en) * | 2008-05-09 | 2011-06-07 | International Business Machines Corporation | Monitoring software pipeline performance on a network on chip |
| US8020168B2 (en) * | 2008-05-09 | 2011-09-13 | International Business Machines Corporation | Dynamic virtual software pipelining on a network on chip |
| US8392664B2 (en) * | 2008-05-09 | 2013-03-05 | International Business Machines Corporation | Network on chip |
| US8494833B2 (en) * | 2008-05-09 | 2013-07-23 | International Business Machines Corporation | Emulating a computer run time environment |
| US20090282211A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines | Network On Chip With Partitions |
| US8214845B2 (en) * | 2008-05-09 | 2012-07-03 | International Business Machines Corporation | Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data |
| US20090282419A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines Corporation | Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip |
| US8230179B2 (en) * | 2008-05-15 | 2012-07-24 | International Business Machines Corporation | Administering non-cacheable memory load instructions |
| US8040799B2 (en) * | 2008-05-15 | 2011-10-18 | International Business Machines Corporation | Network on chip with minimum guaranteed bandwidth for virtual communications channels |
| US8438578B2 (en) * | 2008-06-09 | 2013-05-07 | International Business Machines Corporation | Network on chip with an I/O accelerator |
| US8195884B2 (en) * | 2008-09-18 | 2012-06-05 | International Business Machines Corporation | Network on chip with caching restrictions for pages of computer memory |
| US9170816B2 (en) * | 2009-01-15 | 2015-10-27 | Altair Semiconductor Ltd. | Enhancing processing efficiency in large instruction width processors |
| US8966228B2 (en) * | 2009-03-20 | 2015-02-24 | Arm Limited | Instruction fetching following changes in program flow |
| JP5423156B2 (ja) * | 2009-06-01 | 2014-02-19 | 富士通株式会社 | 情報処理装置及び分岐予測方法 |
| EP2616928B1 (de) * | 2010-09-17 | 2016-11-02 | Soft Machines, Inc. | Mehrfach verzweigte einzelzyklus-vorhersage mit einem latenten cache für frühe und entfernte verzweigungsvorhersage |
| EP2689326B1 (de) | 2011-03-25 | 2022-11-16 | Intel Corporation | Speicherfragmente zur unterstützung einer codeblockausführung mittels durch partitionierbare engines realisierter virtueller kerne |
| WO2012135031A2 (en) | 2011-03-25 | 2012-10-04 | Soft Machines, Inc. | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines |
| CN103649932B (zh) | 2011-05-20 | 2017-09-26 | 英特尔公司 | 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构 |
| WO2012162189A1 (en) | 2011-05-20 | 2012-11-29 | Soft Machines, Inc. | An interconnect structure to support the execution of instruction sequences by a plurality of engines |
| US20150039859A1 (en) | 2011-11-22 | 2015-02-05 | Soft Machines, Inc. | Microprocessor accelerated code optimizer |
| KR101703401B1 (ko) | 2011-11-22 | 2017-02-06 | 소프트 머신즈, 인크. | 다중 엔진 마이크로프로세서용 가속 코드 최적화기 |
| US9632777B2 (en) | 2012-08-03 | 2017-04-25 | International Business Machines Corporation | Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry |
| US9569211B2 (en) | 2012-08-03 | 2017-02-14 | International Business Machines Corporation | Predication in a vector processor |
| US9575755B2 (en) * | 2012-08-03 | 2017-02-21 | International Business Machines Corporation | Vector processing in an active memory device |
| US9594724B2 (en) | 2012-08-09 | 2017-03-14 | International Business Machines Corporation | Vector register file |
| US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
| US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
| US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
| US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
| WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
| US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
| WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
| KR102063656B1 (ko) | 2013-03-15 | 2020-01-09 | 소프트 머신즈, 인크. | 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법 |
| KR102083390B1 (ko) | 2013-03-15 | 2020-03-02 | 인텔 코포레이션 | 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법 |
| WO2023049422A2 (en) * | 2021-09-26 | 2023-03-30 | Ceremorphic, Inc | Core processor and redundant branch processor with control flow attack detection |
| US11921843B2 (en) | 2021-09-26 | 2024-03-05 | Ceremorphic, Inc. | Multi-threaded secure processor with control flow attack detection |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3593306A (en) * | 1969-07-25 | 1971-07-13 | Bell Telephone Labor Inc | Apparatus for reducing memory fetches in program loops |
| US4626988A (en) * | 1983-03-07 | 1986-12-02 | International Business Machines Corporation | Instruction fetch look-aside buffer with loop mode control |
| US4566063A (en) * | 1983-10-17 | 1986-01-21 | Motorola, Inc. | Data processor which can repeat the execution of instruction loops with minimal instruction fetches |
| FR2557712B1 (fr) * | 1983-12-30 | 1988-12-09 | Trt Telecom Radio Electr | Processeur pour traiter des donnees en fonction d'instructions provenant d'une memoire-programme |
| US5131086A (en) * | 1988-08-25 | 1992-07-14 | Edgcore Technology, Inc. | Method and system for executing pipelined three operand construct |
| JPH0475139A (ja) * | 1990-07-18 | 1992-03-10 | Toshiba Corp | ループ並列化装置 |
| JP3032031B2 (ja) * | 1991-04-05 | 2000-04-10 | 株式会社東芝 | ループ最適化方法及び装置 |
| US5898882A (en) * | 1993-01-08 | 1999-04-27 | International Business Machines Corporation | Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage |
| US5485629A (en) * | 1993-01-22 | 1996-01-16 | Intel Corporation | Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines |
| JPH06243036A (ja) * | 1993-02-12 | 1994-09-02 | Hitachi Ltd | キャッシュ制御システム |
| EP0623874A1 (de) * | 1993-05-03 | 1994-11-09 | International Business Machines Corporation | Verfahren zur Ausführung von Befehlen in einer Schleife |
| JP2987311B2 (ja) * | 1995-05-12 | 1999-12-06 | 松下電器産業株式会社 | プロセッサ及び翻訳装置 |
| US5809308A (en) * | 1995-11-17 | 1998-09-15 | Sun Microsystems, Inc. | Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler |
-
1997
- 1997-09-12 US US08/928,444 patent/US6085315A/en not_active Expired - Lifetime
-
1998
- 1998-09-04 JP JP2000512133A patent/JP2001517819A/ja active Pending
- 1998-09-04 KR KR1020007002609A patent/KR20010030587A/ko not_active Application Discontinuation
- 1998-09-04 DE DE69809450T patent/DE69809450T2/de not_active Expired - Lifetime
- 1998-09-04 WO PCT/US1998/018673 patent/WO1999014664A1/en not_active Application Discontinuation
- 1998-09-04 IL IL13445998A patent/IL134459A0/xx unknown
- 1998-09-04 EP EP98946886A patent/EP1012705B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69809450T2 (de) | 2003-07-03 |
| WO1999014664A1 (en) | 1999-03-25 |
| EP1012705B1 (de) | 2002-11-13 |
| EP1012705A1 (de) | 2000-06-28 |
| US6085315A (en) | 2000-07-04 |
| JP2001517819A (ja) | 2001-10-09 |
| IL134459A0 (en) | 2001-04-30 |
| KR20010030587A (ko) | 2001-04-16 |
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| R082 | Change of representative |
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