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Publication numberCN1507048 A
Publication typeApplication
Application numberCN 200310121337
Publication date23 Jun 2004
Filing date11 Dec 2003
Priority date12 Dec 2002
Also published asUS6791361, US20040113657
Publication number200310121337.X, CN 1507048 A, CN 1507048A, CN 200310121337, CN-A-1507048, CN1507048 A, CN1507048A, CN200310121337, CN200310121337.X
InventorsE阿朗, E・阿朗, JL伯恩斯, 伯恩斯, KJ诺瓦卡, 诺瓦卡, RM拉奥, 拉奥
Applicant国际商业机器公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Method and circuit for reducing leakage of grid under the state of dormancy
CN 1507048 A
Abstract  translated from Chinese
一种用于在休眠状态下减轻栅极漏泄的方法和电路。 A gate in the sleep state to reduce the leakage of methods and circuits. 在休眠状态下,可对例如静态电路、动态电路的电路中的多个器件中的一个或多个施加输入模式。 In sleep mode, the input mode can be applied, for example, circuit static circuit, dynamic circuits multiple devices in one or more. 响应该输入模式的施加,该电路中的大多数器件在其每一端,即源极、栅极和漏极端,可以具有基本相同的电压,从而减轻栅极漏泄。 In response to the input pattern is applied, most of the circuit devices at each end thereof, i.e., source, gate and drain terminals, may have substantially the same voltage, thereby reducing gate leakage.
Claims(12)  translated from Chinese
1.一种用于在休眠状态下减轻晶体管栅极漏泄的方法,包含如下步骤:在所述休眠状态下对电路中的第一多个器件中的一个或多个施加输入模式;以及响应所述输入模式的所述施加,在所述电路中的所述第一多个器件中的大多数中的每一个的源极、栅极和漏极端产生基本相同的电压,从而减轻晶体管栅极漏泄。 1. A method for the sleep state to reduce the transistor gate leakage, comprising the steps of: applying a dormant state at the input of the circuit pattern of the first plurality of devices in one or more; and in response to the wherein said input pattern is applied, the source of the circuit in the first plurality of devices in each of the majority, gate, and drain terminal voltage generating substantially the same, so as to reduce transistor gate leakage .
2.如权利要求1所述的方法,其特征在于:所述电路是动态电路。 2. The method according to claim 1, characterized in that: said circuit is a dynamic circuit.
3.如权利要求2所述的方法,其特征在于:通过分别驱动预充电和评估时钟,所述第一多个器件中的所述大多数中的每一个在所述源极、所述栅极和所述漏极端具有基本相同的电压。 3. The method according to claim 2, characterized in that: each driven by the precharge and evaluation clock, the first plurality of devices in each of said plurality of said source electrode, said gate electrode and the drain terminals have substantially the same voltage.
4.如权利要求3所述的方法,其特征在于:通过在所述休眠状态下驱动内部节点到第一状态,所述第一多个器件中的所述大多数中的每一个在所述源极、所述栅极和所述漏极端有基本相同的电压。 4. The method according to claim 3, characterized in that: in said sleep state by driving internal node to the first state, the first plurality of devices in each of said plurality of said the source, the gate and the drain terminal have substantially the same voltage.
5.如权利要求1所述的方法,其特征在于:所述电路是静态电路。 5. The method according to claim 1, characterized in that: said circuit is a static circuit.
6.如权利要求5所述的方法,其特征在于:在所述电路中在晶体管堆中的第二多个器件中的最靠近尾部的一个器件被钝化,从而使亚阈值漏泄的增大减至最小。 6. The method according to claim 5, characterized in that: said circuit transistors in the second plurality of devices in the stack closest to the tail of a device is passivated, thereby the subthreshold leakage increased minimized.
7.一种电路,包含:电源;接地;以及与所述电源和所述接地耦合的第一多个晶体管,其中所述第一多个晶体管中的一个或多个被配置成在休眠状态下接收输入,其中,作为接收的所述输入的结果,在所述多个晶体管中的大多数中的每一个的源极、栅极和漏极端产生基本相同的电压,从而在所述休眠状态下减轻晶体管栅极漏泄。 7. A circuit, comprising: a power supply; ground; and a first plurality of transistors coupled to said power supply and said ground, wherein said first plurality of transistors are arranged one or more in a dormant state receiving an input, wherein, as a result of the input received in the plurality of transistors in a majority of each of the source, a gate and drain terminals generate substantially the same voltage, so that the sleep state, reduce the transistor gate leakage.
8.如权利要求7所述的电路,其特征在于:所述电路是动态电路。 8. The circuit according to claim 7, characterized in that: said circuit is a dynamic circuit.
9.如权利要求8所述的电路,其特征在于进一步包含:与所述第一多个晶体管之一耦合的第一时钟,其中所述第一时钟驱动预充电信号;以及与所述第一多个晶体管之一耦合的第二时钟,其中所述第二时钟驱动评估信号。 9. The circuit according to claim 8, characterized by further comprising: a first plurality of transistors coupled to said first clock, wherein said first clock driver precharge signal; and with the first one of a plurality of transistors coupled to the second clock, wherein said second clock driver evaluation signal.
10.如权利要求9所述的电路,其特征在于进一步包含:与所述电路的内部节点耦合的信号,其中所述信号被配置成在所述休眠状态下驱动所述内部节点到第一状态。 10. The circuit according to claim 9, characterized by further comprising: said internal node and coupled to a signal circuit, wherein said signal is configured to drive the internal node to the first state in the sleep state .
11.如权利要求7所述的电路,其特征在于:所述电路是静态电路。 11. The circuit according to claim 7, characterized in that: said circuit is a static circuit.
12.如权利要求11所述的电路,其特征在于:在所述电路中的晶体管堆中的第二多个晶体管中的最靠近尾部的一个晶体管被钝化,从而使亚阈值漏泄的增大减至最小。 12. The circuit according to claim 11, characterized in that: a second transistor of said plurality of transistors in a transistor circuit in the stack nearest the tail is passivated, thereby the subthreshold leakage increased minimized.
Description  translated from Chinese
用于在休眠状态下减轻栅极漏泄的方法和电路 For reducing gate leakage in sleep mode method and circuit

技术领域 Technical Field

本发明涉及集成电路中的功耗领域,更具体地说,涉及在集成电路工作的休眠方式下减轻晶体管栅极漏泄。 The present invention relates to the field of power integrated circuits, and more particularly, to reduce transistor gate leakage in the integrated circuit to work under the sleep mode.

背景技术 Background

电子器件的功耗可由两部分构成。 The power consumption of electronic devices may be composed of two parts. 动态功耗涉及器件工作时消耗的功率。 Dynamic power when it comes to the work of the power consumed by the device. 对处理器来说,动态功耗可发生在处理器时钟工作时。 For processors, dynamic power can occur when the processor clock. 当设备不在工作时还可能发生漏泄功耗,并按漏泄电流继续消耗功率,该漏泄电流流经构成该电子器件的处于截止状态的晶体管。 When the device is not working are also likely to occur leakage power, according to the leakage current continues to consume power, which constitutes a leakage current flowing through the electronic device is in the OFF state of the transistor.

漏泄电流可包括通常称作“亚阈值漏泄(subthreshold leakage)”和“栅极漏泄(gate leakage)”的漏泄。 Leakage current can include commonly referred to as "subthreshold leakage (subthreshold leakage)" and "gate leakage (gate leakage)" leakage. 亚阈值漏泄可指当晶体管被钝化(deactivated),即截止时在晶体管沟道中流过的电流。 Subthreshold leakage when the transistor is passivated may refer (deactivated), that is, when the cut-off in the current flowing through the transistor channel. 亚阈值漏泄可与阈值电压除以热能(kT)成指数依赖关系。 Subthreshold leakage with a threshold voltage divided by the thermal energy (kT) exponential dependence. 因此,随着阈值电压的降低,亚阈值漏泄也降低。 Thus, with the lower threshold voltage, subthreshold leakage decreases.

“栅极漏泄”电流可指穿过晶体管栅极氧化物的载流子隧道效应。 "Gate leakage" may refer to the current through the carrier tunneling transistor gate oxide. 栅极漏泄可直接与栅极氧化物的尺寸关联。 The gate leakage can be directly associated with the size of the gate oxide. 栅极氧化物越薄,栅极漏泄越大。 The thinner the gate oxide, the greater the gate leakage.

漏泄功耗已成为亚微型晶体管设计中主要关心的问题,特别是在低功率应用中,如便携计算机。 Leakage power has become a submicron transistor design major concern, especially in low-power applications such as portable computers. 例如,在以电池进行工作的便携计算机中,漏泄功耗可缩短电池的寿命。 For example, in a portable computer battery work, the leakage power can shorten battery life. 因此,已经开发了若干技术以减轻漏泄功耗,例如在通常称作“休眠方式”(sleep mode)或“休眠状态”的省电工作方式下减轻漏泄功耗。 Therefore, it has been developed several techniques to reduce the leakage power, for example, often referred to as "sleep mode" (sleep mode) or "hibernate" power-saving way of working to reduce the leakage power.

传统上,减轻功耗技术只集中于漏泄电流的亚阈值部分,因为传统上栅极漏泄一直是总漏泄电流中的不显著部分。 Traditionally, reduce power technology focuses only on part of the subthreshold leakage current, because the traditional gate leakage is the total leakage current has been no significant part. 然而,随着晶体管中的栅极氧化物被做得越来越薄,栅极漏泄增加了,从而使栅极漏泄成为总漏泄电流中的显著部分。 However, as transistor gate oxide is made thinner, the gate leakage is increased, so that the total leakage current gate leakage has become a significant part in.

在Fatih Hamzaoglu等人的题为“Circuit Level Techniques to ControlGate Leakage for sub-100nm CMOS”的论文中已建议了减轻栅极漏泄的构想。 In Fatih Hamzaoglu et al., Entitled "Circuit Level Techniques to ControlGate Leakage for sub-100nm CMOS" articles have been proposed to reduce the gate leakage ideas. 所建议的构想是比N沟道金属氧化物半导体(NMOS)晶体管更多地使用P通道金属氧化物半导体(PMOS)晶体管,因为PMOS栅极漏泄低于NMOS栅极漏泄。 The idea was suggested than an N-channel metal oxide semiconductor (NMOS) transistors greater use of P-channel metal oxide semiconductor (PMOS) transistor, since the gate of PMOS NMOS gate leakage Leakage below. 然而,这造成性能的显著降低。 However, this poses a significant decrease in performance.

所以,在本技术领域需要例如在休眠状态下使晶体管栅极漏泄减至最小而不对性能造成负面影响。 Therefore, the need in the art for example in the sleep state, the transistor gate leakage is minimized without causing a negative impact on performance.

发明内容 DISCLOSURE

在一些实施例中,通过在休眠状态下在电路中的大多数晶体管的源极、栅极和漏极端产生基本相同的电压,上文总结的那些问题至少是可以部分地得到解决。 In some embodiments, by a source in the sleep state in the circuit most transistors, the gate and drain terminals generate substantially the same voltage, those problems summarized above is at least partially resolved.

在本发明的一个实施例中,一种用于在休眠状态下减轻晶体管栅极漏泄的方法可包含如下步骤:在休眠状态下对电路中的多个器件中的一个或多个施加(采用)输入模式(input pattern)。 In one embodiment of the present invention, a method for the sleep state to reduce the transistor gate leakage method may include the steps of: in the sleep state of the circuit multiple devices in one or more of applied (using) Input Mode (input pattern). 作为施加该输入模式的结果,在电路中的大多数器件的源极、栅极和漏极端可产生基本相同的电压,从而减轻栅极漏泄。 As a result of applying the input mode, the source of most of the components of the circuit, a gate and drain terminals can produce substantially the same voltage, thereby reducing gate leakage.

上文已相当宽泛地概括了本发明一个或多个实施例的特征和技术优点,以便使下文中对本发明的详细描述可以得到更好的理解。 The foregoing has outlined rather broadly the present invention, one or more of the features and technical advantages of the embodiments, so that the detailed description below of the present invention may be better understood. 本发明的其他特征和优点将在下文中描述,它们构成本发明权利要求的主题。 Other features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.

附图说明 Brief Description

当结合附图考虑下文的详细描述时,能更好地理解本发明,在这些附图中:图1是栅极漏泄绝对值相对于栅极到源极电压和相对于栅极到漏极电压的变化的示意图; When considering the following detailed description in conjunction of the accompanying drawings, the present invention can be better understood, the accompanying drawings in which: Figure 1 is the absolute value of a gate leakage respect to the gate-to-source voltage and the gate-to-drain voltage with respect to schematic of change;

图2A显示用于减轻静态与非(NAND)电路的栅极漏泄的传统方法;图2B显示采用本发明的原理以减轻静态NAND电路的栅极漏泄;图3A显示传统的NAND动态电路;图3B显示根据本发明配置的修改的NAND动态电路;以及图4是根据本发明的用于在休眠状态下减轻晶体管栅极漏泄的方法的流程图。 2A shows the conventional method with non-static gate leakage (NAND) circuit for reducing; Figure 2B shows the use of the principles of the present invention to mitigate leakage static NAND gate circuit; Figure 3A shows a conventional dynamic NAND circuit; FIG. 3B The present invention is configured to display a modified NAND dynamic circuits based on; and 4 is a flowchart of a method of the present invention is used in sleep mode to reduce the transistor gate leakage FIG.

具体实施方式 DETAILED DESCRIPTION

本发明包含一种用于在休眠状态下减轻晶体管栅极漏泄的方法和电路。 The present invention includes a method and circuit for use in a sleep state to reduce the transistor gate leakage. 在本发明的一个实施例中,在休眠状态下可对电路中的多个器件中的一个或多个施加输入模式,该电路如静态电路、动态电路。 In one embodiment of the present invention, in sleep mode can be applied to the circuit input mode multiple devices in one or more of the circuit such as static circuits, dynamic circuits. 响应这一输入模式的施加,电路中的大多数器件可在其每一端,即源极、栅极和漏极端,具有基本相同的电压,从而减轻栅极漏泄。 In response to this input pattern is applied, most of the circuit devices at each end thereof, i.e., source, gate and drain terminals, having substantially the same voltage, thereby reducing gate leakage. 应该注意,尽管在下文中结合了3输入静态NAND电路和2输入动态NAND电路来讨论本发明,但本发明的原理可在任何类型的静态或动态电路中实现。 It should be noted that although a combination of 3-input NAND circuit static and dynamic 2-input NAND circuit is discussed below in the present invention, the principles of the present invention may be implemented in any type of static or dynamic circuit. 还应注意,实现这些静态或动态电路的实施例应落入本发明的范围之内。 It should also be noted that these embodiments static or dynamic circuits shall fall within the scope of the present invention.

在下文的讨论中,陈述了大量具体细节以提供对本发明的透彻理解。 In the following discussion, numerous specific details are set forth in order to provide a thorough understanding of the present invention. 然而,应该注意,本领域技术人员能实施本发明而无需这些具体细节。 However, it should be noted that the skilled person to practice the invention without these specific details. 在其他实例中,以方框图的形式显示公知的电路,以免因不必要的细节模糊了本发明。 In other instances, well-known show in block diagram form the circuit, so as to avoid unnecessary detail obscure the present invention.

如在背景技术部分中说明的那样,减轻漏泄电流的传统技术只集中于漏泄电流的亚阈值部分,因为栅极漏泄在传统上一直是总漏泄电流的不显著部分。 As to reduce the leakage current of conventional techniques such as described in the Background section is only focused on part of the sub-threshold leakage current, gate leakage because traditionally been insignificant part of the total leakage current. 然而,晶体管中的栅极氧化物已被做得越来越薄,从而使栅极漏泄成为总漏泄电流的显著部分。 However, the transistor gate oxide is made thinner, so that the gate leakage has become a significant part of the total leakage current. 因此,本技术领域需要使晶体管栅极漏泄减至最小。 Thus, the need in the art to make the transistor gate leakage is minimized.

栅极漏泄是穿过栅极氧化物的电场的指数函数。 The gate leakage is an electric field across the gate oxide of the exponential function. 就是说,如图1中所示,栅极漏泄是栅极到源极和栅极到漏极电压的指数函数。 That is, as shown in FIG. 1, the gate leakage is the gate to source and gate to drain voltage of the exponential function. 图1显示栅极漏泄的绝对值相对于栅极到源极电压(“Vgs”)和相对于栅极到漏极电压(“Vg”)的变化。 Figure 1 shows the absolute value of the gate leak with respect to the gate-to-source voltage ("Vgs") with respect to the gate to drain voltage ("Vg") changes. 如图1中所示,当n型晶体管被激活时(这发生在Vgs为高电平时),当Vgd为高电平时被激活的晶体管的栅极漏泄电流产生最大值。 As shown in Figure 1, when the n-type transistor is activated (this happens when Vgs is high), when the gate leakage current is high Vgd activated transistors generate maximum. 也如图1所示,当n型晶体管被钝化时(这发生在Vgs为低电平),当Vgd为最大值时栅极漏泄电流为最大值。 Also shown in Figure 1, when the n-type transistor is deactivated (This occurs when Vgs is low), when Vgd is maximum gate leakage current is maximum. 因此,为减小栅极漏泄电流,可能需要产生比较低的Vgs和Vgd的幅值。 Therefore, to reduce gate leakage current may need to produce a relatively low magnitude of Vgs and Vgd. 这可通过在晶体管的源极、漏极和栅极端产生基本相同的电压来实现。 This can be a drain, and a gate terminal of the voltage generated to achieve substantially the same at the source of the transistor. 下面将结合图2A-B、图3A-B及图4来讨论通过在电路中的大多数晶体管的源极、漏极和栅极端产生基本相同的电压来在电路的休眠工作状态下减轻栅极漏泄。 Below in conjunction with FIG. 2A-B, Figures 3A-B and 4 discussed in the circuit by the source of most transistors, drain and gate terminals to generate substantially the same voltage at the gate to reduce dormant state of the circuit leakage. 图2A显示使3输入静态NAND电路的漏泄电流减至最小的传统方法。 Figure 2A shows make 3 input NAND circuit static leakage current to minimize the traditional methods. 图2B显示采用本发明的原理以减轻3输入静态NAND电路的栅极漏泄,从而使总漏泄功耗的减少量大于传统方法的减少量。 2B shows the use of the principles of the present invention is to mitigate the static three input NAND gate leakage circuit, thereby reducing the total leakage power is larger than the conventional method of reduction. 图3A显示传统的2输入动态NAND电路。 Figure 3A shows a conventional 2-input NAND circuit dynamic. 图3B显示采用本发明原理以减轻栅极漏泄的修改后的2输入动态NAND电路。 3B shows the use of the principles of the present invention to alleviate 2-input NAND circuit dynamically modify the gate leakage after. 图4是用于减轻图2A所示静态电路和图3A所示动态电路的栅极漏泄的方法的流程图。 Figure 4 is a flow chart Fig. 3A gate of dynamic circuits leak a method for reducing the static circuit shown in FIG. 2A and FIG.

图2A-B-静态电路图2A-B显示3输入NAND电路200。 Figure 2A-B- static circuit diagram 2A-B show 3-input NAND circuit 200. 电路200可包含电源201,该电源在节点205与p型晶体管202、203及204耦合。 Circuit 200 may comprise a power source 201, 202, 203 and 204 is coupled to the power source node 205 and the p-type transistor. p型晶体管202、203及204可在节点207与n型晶体管206耦合。 202, 203 and 204 may be coupled to the p-type transistor 206 at node 207 and the n-type transistor. n型晶体管206可与n型晶体管208、209串联耦合。 208, 209 may be n-type transistor 206 coupled in series with the n-type transistor. n型晶体管209可与接地210耦合。 n-type transistor 209 may be coupled to the ground 210.

如前所述,图2A显示减轻电路200的漏泄电流的传统方法。 As described above, FIG. 2A shows the conventional method to alleviate leakage current circuit 200. 参考图2A,可在休眠状态下对输入A,B和C施加输入模式0,0,0,着眼于减轻亚阈值漏泄。 2A, there can be in sleep mode for input A, B and C applied to input mode 0,0,0, focusing on the reduction of the subthreshold leakage. 在休眠状态下,通过施加这样的输入模式,晶体管202、203及204可被激活,即导通,而晶体管206、208及209可被钝化,即截止。 In the sleep state, by applying this input mode, transistors 202, 203 and 204 may be activated, ie turned on, while transistors 206, 208 and 209 can be passivated, ie off. 节点205和207具有高电位。 Nodes 205 and 207 has a high potential. 通过钝化晶体管206、208及209,电路200的输出变为高电平,从而使晶体管202、203及204通过它们的栅极漏泄,如箭头211、212及213分别指出的那样。 By passivating the transistors 206, 208 and 209, the output circuit 200 goes high, so that the transistors 202, 203 and 204 by their gates leakage, as indicated by arrows 211, 212 and 213, respectively, as indicated. 再有,位于节点207附近的n型晶体管,即n型晶体管206,具有高的Vgd和低的Vgs,从而造成显著的栅极漏泄电流。 Further, a node located near the n-type transistor 207, i.e., n-type transistor 206, having a high and low Vgd Vgs, resulting in a significant gate leakage current. 尽管通过施加这一输入模式可减小亚阈值漏泄,但晶体管202、203、204及206会产生栅极漏泄。 Although by applying the input mode to reduce subthreshold leakage, but transistor 202, 203 and 206 will have a gate leakage. 如下文中结合图2B讨论的那样,通过在大多数晶体管的源极、漏极和栅极端产生基本相同的电压,图2A的电路200中的栅极漏泄可得到减轻。 As described below in connection FIG. 2B discussed by the source of most of the transistor, a drain and a gate terminal to generate substantially the same voltage, circuit 200 of FIG. 2A gate leakage mitigation available.

如前所述,图2B显示采用本发明的原理以减轻电路200中的栅极漏泄。 As described above, FIG. 2B shows the use of the principles of the present invention to mitigate the gate leakage circuit 200. 参考图2B,可在休眠状态下对输入A′、B′和C′施加输入模式1,1,0。 2B, the can is in sleep mode for input A ', B' and C 'is applied to the input mode 1,1,0. 在休眠状态下,通过施加这一输入模式,晶体管202、203及209可被钝化,而晶体管204、206及208可被激活。 In the sleep state, by applying the input mode, the transistors 202, 203 and 209 can be passivated, and transistors 204, 206 and 208 can be activated. 节点205和207具有高电位。 Nodes 205 and 207 has a high potential. 通过只钝化最靠近晶体管堆(transistor stack)(晶体管206、208及209)尾部的晶体管209,电路200在节点207的输出变为近似于Vdd,即电源201的电压电平。 Only through the passivation stack closest transistor (transistor stack) (transistors 206, 208 and 209) the tail transistor 209, the circuit 200 at the output node 207 becomes approximately Vdd, i.e., the voltage level of the power supply 201. 于是,晶体管202和203可在它们的所有端,即Vgs和Vgd,有基本相同的电压。 Thus, transistors 202 and 203 in all their ends, namely Vgs and Vgd, have substantially the same voltage. 通过使它们的所有端具有相同电压,晶体管202和203的栅极漏泄可基本上接近于零。 By making all their ends have the same voltage, the transistor 202 and the gate leakage 203 can be substantially close to zero. 就是说,通过使它们的所有端具有相同电压,Vgs和Vgd可为最小值,造成近乎为零的栅极漏泄。 That is, by making all their ends have the same voltage, Vgs and Vgd for the minimum, resulting in near-zero gate leakage. 再有,在晶体管206和208的端的电压,即Vgs和Vgd,基本相同,从而减小栅极漏泄。 Further, in the transistor 206 and the voltage terminal 208, i.e., Vgs and Vgd, substantially identical, thereby reducing gate leakage. 因此,晶体管202、203、206和208的栅极漏泄可基本为零。 Therefore, the transistor gate leakage 202,203,206 and 208 can be substantially zero. 现在显著量的栅极漏泄只发生于晶体管204,如箭头213所示。 Now a significant amount of gate leak occurs only on the transistor 204, as shown by arrow 213. 少量栅极漏泄可发生于晶体管209。 A small amount of leakage can occur at the gate of the transistor 209. 于是,电路200的总栅极漏泄已被减小。 Thus, the total gate leakage circuit 200 is reduced. 再有,由于在晶体管堆(晶体管206、208和209)中最低位置的晶体管209已被钝化,亚阈值漏泄的增加可减至最小。 Further, since the transistor stack (transistors 206, 208 and 209) of the transistor 209 in the lowest position has been passivated, the subthreshold leakage increased can be minimized. 因此,与图2A中的电路200相比,图2B中的电路200的总漏泄电流可被减小。 Thus, as compared with 200 in FIG. 2A circuit, in FIG. 2B total leakage current circuit 200 can be reduced.

图3A-传统的动态电路图3A显示传统的2输入NAND动态电路300。 3A- conventional dynamic circuit diagram in Figure 3A shows a conventional 2-input NAND circuit 300 dynamically. 电路300可包含电源301,该电源与p型晶体管302、303耦合。 Circuit 300 may comprise a power supply 301, 302, 303 coupled to the power supply and the p-type transistor. 电源301可进一步与输出反相器耦合,该输出反相器包含p型晶体管304,该p型晶体管304与n型晶体管305串联耦合。 Power supply 301 may be further coupled to the output of the inverter, the output of the inverter comprises a p-type transistor 304, 305 is coupled in series to the p-type transistor 304 and n-type transistor. 电路300在节点306的输出可与p型晶体管303的栅极耦合。 Circuit 300 at the output node 306 may be coupled to the gate of the p-type transistor 303. 动态节点307可与晶体管304、305的栅极以及p型晶体管302、303和n型晶体管308的漏极耦合。 Dynamic node with the gate of transistor 307 and the p-type and n-type transistors 302, 303, 304, 305 of transistor 308 is coupled to the drain. n型晶体管308可与n型晶体管309、310串联耦合。 309, 310 may be n-type transistor 308 coupled in series with the n-type transistor. n型晶体管310和305可与接地311耦合。 n-type transistors 310 and 305 can be coupled to the ground 311. 时钟信号可输入到晶体管302(“预充电晶体管”)和晶体管310。 Clock signal can be input to the transistor 302 ("precharge transistor") and a transistor 310. 晶体管308和309可接收来自前面耦合的动态电路的输出,如“A”和“B”指示的那样。 Transistors 308 and 309 can receive dynamic circuit from an output coupled to the front, as "A" and "B" indication. 在一个实施例中,晶体管304、308、309及310可被配置成有比晶体管305更宽的栅极区。 In one embodiment, transistors 304,308,309 and 310 may be configured to have a wider than the gate region of the transistor 305.

如电路300这样的动态电路被设计成以两阶段工作,即预充电阶段和评估阶段。 Such a dynamic circuit such as circuit 300 is designed to work in two stages, namely the pre-charge phase and the evaluation phase. 在预充电阶段,如电路300这样的动态电路的节点被设置成预先定义的电压电平。 In the precharge phase, such as the dynamic circuits node circuit 300 is set to a predefined voltage level. 在评估阶段,根据该动态转换电路的逻辑功能,这些动态电路节点从它们的预充电状态进行转换。 During the assessment phase, according to the dynamic logic conversion circuit, the dynamic circuit node to convert from their pre-charge state. 参考图3A,在预充电阶段,时钟信号(CLK)可具有低电位值,即“0”,从而使动态节点307具有高电位值,即二进制值“1”。 3A, the precharge phase, the clock signal (CLK) may have a low potential value, that is, "0", so that the dynamic node 307 having a high potential level, i.e. the binary value "1." 在评估阶段,CLK可具有高电位值,即二进制值“1”,从而使动态节点307具有低电位值,即二进制值“0”。 During the assessment phase, CLK may have a high potential level, i.e. the binary value "1", so that the dynamic node 307 has a low potential value, i.e. the binary value "0."

在休眠状态下,时钟信号(CLK)可被设置为处于预充电阶段或处于评估阶段。 In sleep mode, the clock signal (CLK) can be set in the pre-charge stage or in the evaluation stage. 如果在休眠状态下采用评估阶段,则如上所述,CLK为“1”,从而使得在节点307出现0值,在输出节点306出现二进制值“1”。 If the assessment phase in the sleep state, as described above, CLK is "1", so that the value 0 in node 307 appears at the output node 306 appears binary value "1." 假定与电路300耦合的其他动态电路也处在评估阶段,则到其他动态电路的输出也具有二进制值“1”。 Assumptions and other dynamic circuit coupled to circuit 300 is also at the evaluation stage, the output of the circuit to the other dynamic also has a binary value of "1." 因此,输入A和B具有二进制值“1”。 Therefore, the input A and B has a binary value of "1." 由于动态节点具有低电位值,所以到输出反相器的输入近似于零。 Due to the dynamic node having a low potential level, so that the input to the output of the inverter approximately zero. 于是,晶体管304、308、309和310被激活,即导通。 Thus, the transistors 304,308,309 and 310 are activated, that is turned on. 晶体管302、303和305被钝化,即截止。 Transistors 302, 303 and 305 are passivated, that is turned off. 在晶体管304、308、309和310中可发生显著的栅极漏泄量,因为在各端,即Vgs和Vgd的电压电平不相等,从而造成显著的栅极漏泄电流。 It can occur a significant amount of gate leakage in transistors 304,308,309 and 310, because in the end, that is Vgs and Vgd unequal voltage levels, resulting in a significant gate leakage current. 在晶体管302和305中可发生不那么显著的栅极漏泄量,因为栅极和漏极端之间的电压电平不相等。 It may occur no less significant amount of gate leakage transistor 302 and 305, because the voltage level between the gate and drain terminals are not equal. 再有,可由被钝化的晶体管302、304和305可产生亚阈值漏泄而且该漏泄可能是显著的。 Further, the transistors 302, 304 may be passivated and 305 may produce subthreshold leakage and that the leak may be significant. 如下文讨论的那样,在休眠状态下使用预充电阶段可减小电路300的亚阈值漏泄及栅极漏泄。 As discussed above, the use of pre-charge stage in sleep mode can reduce subthreshold leakage and gate leakage circuit 300.

如果在休眠状态下使用预充电阶段,则如上所述,CLK是“0”,从而使得在节点307出现二进制值“1”,在输出节点306出现值“0”。 If you use the pre-charge stage in sleep mode, as described above, CLK is "0", so that the node 307 appears binary value "1" appears at the output node 306 the value "0." 假定与电路300耦合的其他动态电路也处在预充电阶段,则到其他动态电路的输出也为“0”。 Assumptions and other dynamic circuit coupled to circuit 300 is also at the pre-charge stage, then to other dynamic circuit of the output is "0." 因此,输入A和B为“0”。 Therefore, the input A and B is "0." 由于动态节点具有高电位值,所以到输出反相器的输入近似于Vdd,即电源301的电位。 Due to the dynamic node having a high potential level, so that the input to the output of the inverter approximately Vdd, i.e., the potential of the power supply 301. 因此,晶体管302、303和305被激活,即导通。 Thus, the transistors 302, 303 and 305 are activated, that is turned on. 晶体管304、308、309和310被钝化,即截止。 Transistors 304,308,309 and 310 are passivated, that is turned off. 在预充电晶体管302和晶体管305中可发生显著的栅极漏泄量,因为在它们的端,即Vgs和Vgd的电压电平不相等,从而造成显著的栅极漏泄电流。 Precharge transistor 302 and transistor 305 significant amount of gate leakage can occur, because at their ends, namely Vgs and Vgd unequal voltage levels, resulting in a significant gate leakage current. 因为栅极和漏极的端之间的电压电平不相等,在晶体管304和308中可能发生不那么显著的栅极漏泄量。 Since the voltage level between the gate and drain terminals are not equal, less significant amount of leakage may occur in the gate of the transistor 304 and 308. 再有,晶体管304的亚阈值漏泄可能是显著的,晶体管304可能配置有宽沟道。 Further, the value of sub-threshold leakage transistor 304 may be significant, the transistor 304 may be configured with a wide channel. 尽管在休眠状态下通过使用预充电阶段代替评估阶段可减小栅极漏泄和亚阈值漏泄,但使用如下文讨论的本发明原理可在电路300中进一步减小栅极漏泄而同时具有类似的亚阈值漏泄。 While in the sleep state instead of by using the precharge phase evaluation stage can reduce gate leakage and subthreshold leakage, but discussed using the following principles of the present invention can be further reduced gate leakage in circuit 300 and also has a similar sub threshold leakage.

图3B-修改的动态电路图3B显示根据本发明配置的修改的2输入NAND动态电路350。 3B- Figure 3B shows a circuit diagram of a modified dynamic dynamic NAND circuit 350 according to the second input of the present invention is configured to modify. 动态电路350可类似于电路300(图3A)来配置,除可使用单独的预充电和评估时钟来钝化预充电和评估晶体管以外。 Dynamic circuit 350 may be similar to circuit 300 (FIG. 3A) to configure, in addition to using a separate precharge and evaluation clocks passivated transistor precharge and evaluate outside. 再有,动态节点307可由最小尺寸的有条件上拉晶体管(conditional pull-up transistor)313充电。 Further, the dynamic node 307 may be conditional minimum size pull-up transistor (conditional pull-up transistor) 313 is charged. 再有,输出反相器配置可修改成通过使用另一个最小尺寸的晶体管314断开n型晶体管305的下拉(pull down)通路来上拉(pull up)输出反相器的输入。 Further, the output of inverter configuration can be modified by using another minimum size of transistor 314 off 305 n-type pull-down transistor (pull down) path to the pull (pull up) the output of the inverter input. 再有,可使用休眠状态信号来激活p型晶体管313、315,从而保证动态节点307和内部节点306被拉高。 Furthermore, can be activated using p-type transistors 313,315 hibernation signal, thereby ensuring dynamic node 307 and internal node 306 is pulled high. 在休眠状态下,休眠状态信号可用于通过驱动内部节点312到低电平以激活p型晶体管313、315。 In sleep mode, hibernation signal can be used by driving internal node 312 to a low level in order to activate the p-type transistors 313,315.

参考图3B,电路350可包括与电路300(图3A)相比的如下额外的部件。 3B, the circuit 350 may include the following additional components to the circuit 300 (FIG. 3A) compared. 节点312可耦合于p型晶体管313,该晶体管313耦合于晶体管309的漏极和晶体管308的源极。 Node 312 may be coupled to the p-type transistor 313, the transistor 313 is coupled to the source of transistor 309 and the drain electrode of the transistor 308. p型晶体管313的源极可与电源301耦合。 313 p-type transistor source electrode 301 is coupled with the power supply. 再有,节点312可与n型晶体管314耦合,而该晶体管314耦合于晶体管305的源极。 Further, 312 may be coupled with the n-type transistor 314 nodes, the transistor 314 is coupled to the source electrode of transistor 305. n型晶体管314的源极可与接地311耦合。 314 n-type transistor source electrode 311 is coupled with the ground. 在n型晶体管314的漏极和晶体管305的源极处的节点可与p型晶体管315耦合。 In the n-type transistor drain node 314 and the source electrode of the transistor 305 and the p-type transistor 315 may be coupled. p型晶体管315的源极可与电源301耦合。 315 p-type transistor source electrode 301 is coupled with the power supply. 在一个实施例中,添加到电路300(图3A)的晶体管313、314和315可以是具有不显著的栅极区的最小尺寸器件。 In one embodiment, added to the circuit 300 (FIG. 3A) of the transistors 313, 314 and 315 may be a device having a smallest dimension no significant gate region. 应该注意,电路350可包含替代装置和/或配置以实现上述使用本发明原理所进行的修改。 It should be noted, circuit 350 may include alternative means and / or modify the configuration in order to achieve the above using the principles of the present invention is carried out. 还应注意,本领域普通技术人员将能实现这样的实施例,而且这些实施例将落入本发明的范围之内。 It should also be noted that one of ordinary skill in the art will be able to achieve such embodiments, but these embodiments are intended to fall within the scope of the present invention.

再参考图3B,如果在休眠状态下预充电阶段时钟具有二进制值“1”,评估阶段时钟具有值“0”,而休眠状态信号的补码具有值“0”(休眠状态信号有效),则在电路350中的大量节点达到高电位值,从而减轻电路300(图3A)中的栅极漏泄。 Referring again to Figure 3B, if in the sleep state precharge phase clock has a binary value of "1", the assessment phase clock has a value of "0" signal dormant complement has the value "0" (dormant signal is valid), then In a large number of nodes in the circuit 350 reaches a high potential level, so as to reduce the circuit 300 (FIG. 3A) in the gate leakage. 就是说,如果在休眠状态下预充电阶段时钟有二进制值“1”,评估阶段时钟具有值“0”,而休眠状态信号的补码具有值“0”,则在电路350中的大多数晶体管在其源极、漏极和栅极端可具有基本相同的电压,从而减轻电路300(图3A)中的栅极漏泄。 That is, if in the sleep state precharge phase clock has a binary value of "1", the assessment phase clock has a value of "0" signal dormant complement has the value "0" in the circuit 350 Most transistor at its source, drain and gate terminals may have substantially the same voltage, thereby reducing the circuit 300 (FIG. 3A) in the gate leakage.

如果在休眠状态下休眠状态信号的补码具有值“0”,则节点312达到值0。 If the sleep status signal complement has the value "0" in the sleep state, the node 312 reaches a value of zero. 于是,晶体管313和315被激活,即导通,而晶体管314被钝化,即截止。 Thus, the transistors 313 and 315 are activated, i.e. turned on, and the transistor 314 is deactivated, i.e., turned off. 再有,如果预充电阶段时钟具有二进制值“1”而评估阶段时钟具有值“0”,则晶体管302和310被钝化。 Further, if the precharge phase clock having a binary value of "1" and assessment phase clock has a value "0", the transistors 302 and 310 are passivated. 节点306和307达到二进制值“1”。 Nodes 306 and 307 reaches a value of binary "1." 于是,晶体管305被激活,而晶体管303、304被钝化。 Thus, transistor 305 is activated, and the transistor 303, 304 are passivated. 假定电路350与其他类似设计的动态电路耦合,则那些其他动态电路的输出也是二进制值“1”。 Assumed circuit 350 is coupled with other similar dynamic circuits design, the output of those other dynamic circuit is a binary value of "1." 因此,输入A和B是二进制值“1”。 Therefore, the input A and B is a binary value of "1." 于是,晶体管308和309被激活。 Thus, the transistors 308 and 309 are activated. 上述情况的结果是,晶体管302、303、304、305、308及309在它们的所有各端,即Vgs和Vgd具有相同电压(二进制值“1”)。 The results of the above is that the transistor 302,303,304,305,308 and 309 in all their respective ends, which has the same voltage Vgs and Vgd (binary "1"). 通过在它们的所有端具有相同电压,晶体管302、303、304、305、308及309的栅极漏泄可基本上接近于零。 By all their ends have the same voltage, transistor gate leakage 302,303,304,305,308 and 309 may be substantially close to zero. 在晶体管310中可发生少量栅极漏泄,在该晶体管中漏极(高电位)和栅极(低电位)具有不同的电位。 A small amount of leakage may occur in the gate of the transistor 310, the transistor drain (high potential) and the gate (low potential) having different potentials. 再有,在晶体管313、314及315中可发生不显著的栅极漏泄量,因为它们可以是带有不显著的栅极区的最小尺寸的器件。 Further, no significant amount of gate leak may occur in the transistors 313, 314 and 315, as they may be the minimum size of the device with no significant region of the gate. 晶体管313和315可显示出比晶体管314更大的栅极漏泄量,因为其源极和漏极具有高电位而栅极具有低电位。 Transistors 313 and 315 may exhibit greater than the transistor 314 gate leakage amount, because of its source and drain having a high potential and the gate has a low potential. 晶体管314的源极和栅极具有低电位而晶体管314的漏极具有高电位。 Source and gate of the transistor 314 has a low potential while the drain of the transistor 314 has a high potential. 因此,通过使大多数晶体管的端,即Vgs和Vgd,处于基本相同的电位,可减小电路300(图3A)的栅极漏泄。 Thus, by making the most of the transistor side, i.e. Vgs and Vgd, at substantially the same potential, can reduce the circuit 300 (FIG. 3A) of the gate leakage. 再有,当在休眠状态下使用预充电阶段时,电路350的亚阈值漏泄近似等于电路300(图3A)的亚阈值漏泄。 Further, when the precharge phase in the sleep state, the circuit 350 is approximately equal to the subthreshold leakage circuit 300 (FIG. 3A) of the subthreshold leakage. 亚阈值漏泄可在预充电晶体管302以及晶体管314中发生。 Subthreshold leakage may occur in the precharge transistor 302 and a transistor 314. 因此,与图3A中的电路300相比,图3B中的电路350的总漏泄电流减小了。 Thus, as compared with the circuit 300 in FIG. 3A, the total leakage current of the circuit 350 in FIG. 3B is reduced.

图4-用于减轻晶体管栅极漏泄的方法图4是本发明一个实施例的方法400的流程图,该方法400用于在休眠状态下减轻在例如静态电路、动态电路的电路中的晶体管栅极漏泄。 Figure 4 - to reduce the transistor gate leakage method 4 is a flow diagram for one embodiment of the invention the method 400, the method 400 is used to relieve the sleep state, for example, circuit static circuit, dynamic circuits transistor gate pole leakage.

参考图4并结合图2A-B及图3A-B,在步骤401中,在休眠状态下可对例如静态电路200、动态电路350的电路中的多个器件中的一个或多个施加输入模式。 Referring to Figure 4 in conjunction with Figures 2A-B and Figure 3A-B, in step 401, in the sleep state can, for example, a static circuit 200, a dynamic circuit 350 of the circuit multiple devices in one or more of the applied input mode . 参考图2B,在休眠状态下,可对输入A′、B′和C′施加输入模式1,1,0。 2B, the in the sleep state, the input A ', B' and C 'is applied to the input mode 1,1,0. 参考图3B,输入A和B可接收二进制值1。 3B, the input A and B may receive a binary value of one. 预充电阶段时钟可具有二进制值1,而评估阶段时钟可具有值0。 Precharge clock phase may have a binary value of 1, and the evaluation phase clock may have a value of 0. 在休眠状态下,可启动休眠状态信号,从而对电路350的内部节点充电。 In the sleep state, it can start a dormant state signal, thereby charging circuit 350 internal nodes.

在步骤402中,响应输入模式的施加,可在例如静态电路200、动态电路350的电路中的多个晶体管的大多数中的源极、栅极和漏极端产生基本相同的电压。 In step 402, in response to the input mode is applied, such as static circuit 200 may be, the source of most dynamic circuit 350 of the circuit in a plurality of transistors, a gate and drain terminals generate substantially the same voltage. 参考图2B,在休眠状态下,通过对输入A′、B′和C′施加输入模式1,1,0,晶体管202、203和209可被钝化,而晶体管204、206和208可被激活。 2B, the in the sleep state, the input A ', B' and C 'is applied to the input mode 1,1,0, transistors 202, 203 and 209 can be passivated, and the transistors 204, 206 and 208 can be activated . 节点205和207具有高电位。 Nodes 205 and 207 has a high potential. 通过只钝化最靠近晶体管堆(晶体管206、208和209)尾部的晶体管209,电路200在节点207的输出近似于Vdd,即电源201的电压电平。 Only through the passivation stack closest transistor (transistors 206, 208 and 209) the tail transistor 209, the circuit 200 at the output node 207 similar to Vdd, i.e., the voltage level of the power supply 201. 于是,晶体管202、203、206和208在它们的所有端,即Vgs和Vgd具有基本相同的电压。 Thus, the transistors 202,203,206 and 208 in all their ends, namely Vgs and Vgd have substantially the same voltage. 通过在其所有端具有基本相同的电压,晶体管202、203、206和208的栅极漏泄可基本上接近于零。 By all their ends having substantially the same voltage, transistors 202,203,206 and 208 of the gate leakage can be substantially close to zero. 现在显著的栅极漏泄量只发生于晶体管204。 A significant amount of gate leakage current occurs only in the transistor 204. 少量栅极漏泄可发生于晶体管209。 A small amount of leakage can occur at the gate of the transistor 209. 于是,减小了图2A中的电路200的总栅极漏泄。 Thus, reducing the total gate Fig. 2A leakage circuit 200. 再有,由于在晶体管堆(晶体管206、208和209)中最低位置的晶体管209被钝化,亚阈值漏泄的增加可减至最小。 Further, since the transistor stack (transistors 206, 208 and 209) in the lowest position of the transistor 209 is deactivated, the subthreshold leakage increased can be minimized. 因此,与图2A中的电路200相比,图2B中的电路200的总漏泄电流被减小。 Thus, as compared with 200 in FIG. 2A circuit, in FIG. 2B total leakage current circuit 200 is reduced.

参考图3B,对电路350施加输入模式的结果是,晶体管302、303、304、305、308及309可在它们的所有端,即Vgs和Vgd具有基本相同的电压(二进制值“1”)。 Results 3B, the circuit 350 is applied to the input mode transistor 302,303,304,305,308 and 309 in all their ends, namely Vgs and Vgd have substantially the same voltage (binary "1"). 通过在它们的所有端具有基本相同的电压,晶体管302、303、304、305、308及309的栅极漏泄可基本上接近于零。 By all their ends having substantially the same voltage, transistor gate leakage 302,303,304,305,308 and 309 may be substantially close to zero. 在晶体管310中可发生少量的栅极漏泄,在该晶体管中漏极(高电位)和栅极(低电位)具有不同的电位。 A small amount of leakage may occur in the gate of the transistor 310, the transistor drain (high potential) and the gate (low potential) having different potentials. 再有,在晶体管313、314及315中可发生不显著的栅极漏泄量,因为它们可以是带有不显著的栅极区的最小尺寸的器件。 Further, no significant amount of gate leak may occur in the transistors 313, 314 and 315, as they may be the minimum size of the device with no significant region of the gate. 因此,通过使大多数晶体管的各端,即Vgs和Vgd,处于基本相同的电位,电路300(图3A)的栅极漏泄可被减小。 Thus, by making the most of each side of the transistor, i.e. Vgs and Vgd, at substantially the same potential, the circuit 300 (FIG. 3A) of the gate leakage can be reduced. 再有,当在休眠状态下使用预充电阶段时,电路350的亚阈值漏泄近似等于电路300(图3A)的亚阈值漏泄。 Further, when the precharge phase in the sleep state, the circuit 350 is approximately equal to the subthreshold leakage circuit 300 (FIG. 3A) of the subthreshold leakage. 亚阈值漏泄可在预充电晶体管302以及晶体管314中发生。 Subthreshold leakage may occur in the precharge transistor 302 and a transistor 314. 因此,与图3A中的电路300相比,图3B中的电路350的总漏泄电流减小了。 Thus, as compared with the circuit 300 in FIG. 3A, the total leakage current of the circuit 350 in FIG. 3B is reduced.

应该注意,方法400可以以不同的给出顺序执行,在图4的讨论中给出的顺序是示例性的。 Should be noted that the method 400 may be performed in a different order is given, the order given in the discussion of FIG. 4 are exemplary. 还应注意,图4中的某些步骤是可几乎并行执行的。 It should also be noted that some of the steps in Figure 4 are almost parallel.

尽管结合若干实施例描述了该电路和该方法,但不是要限定于这里陈述的特定形式;相反,而是要覆盖这些替代物、修改和等效物,这些替代物、修改和等效物有理由被包括在所附权利要求书规定的本发明的精神和范围之内。 Although described with reference to several embodiments of the circuit and the method, but it is not intended to be limited to the particular form set forth herein; rather, but to cover such alternatives, modifications and equivalents, such alternatives, modifications and equivalents have grounds are included within the spirit and scope of the appended claims and the provisions of the present invention. 应该注意,那些小标题只是用于组织目的,不意味着限制说明书或权利要求书的范围。 It should be noted that sub-headings are for organizational purposes only, not intended to limit the scope of the specification or claims requirements.

Classifications
International ClassificationH03K19/00, H01L21/822, H01L27/04, H01L21/335
Cooperative ClassificationH03K19/0016
European ClassificationH03K19/00P6
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