CN104483611B - Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device - Google Patents
Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device Download PDFInfo
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- CN104483611B CN104483611B CN201410681403.7A CN201410681403A CN104483611B CN 104483611 B CN104483611 B CN 104483611B CN 201410681403 A CN201410681403 A CN 201410681403A CN 104483611 B CN104483611 B CN 104483611B
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Abstract
The invention discloses a device for testing bias temperature instability degrading of a MOS (metal oxide semiconductor) device. The device comprises a to-be-tested circuit, a reference calibration circuit and a detection circuit, wherein the output ends of the to-be-tested circuit and the reference calibration circuit are simultaneously connected with the detection circuit, a first feedback control assembly and a first Schmitt trigger are arranged in the to-be-tested circuit, the first feedback control assembly is used for applying stress on to-be-tested feedback loop components in the first Schmitt trigger so as to generate degrading, the to-be-tested circuit is used for outputting degraded actual hysteresis voltage signals, the reference calibration circuit is used for outputting standard hysteresis voltage signals, and the detection circuit is used for comparing and measuring the difference between the actual hysteresis voltage signals and the reference standard hysteresis voltage signals, so as to test the degrading degree of the feedback loop components. The device has the characteristics that the NBTI (negative bias temperature instability) and PBTI (positive bias temperature instability) properties can be tested, the circuit structure is simple, and the testing accuracy is high. The invention discloses a method for testing the bias temperature instability degrading of the MOS device.
Description
Technical field
The invention belongs to semiconductor device reliability technical field, more particularly to a kind of MOS device Bias Temperature is not
The test device of stabilization sexual involution.
Background technology
As semiconductor process technique enters deep sub-micron era, Negative Bias Temperature Instability (NBTI) turns into influence device
One of the principal element in part performance degradation and life-span.NBTI effects refer to apply minus gate voltage to PMOS device at high temperature and cause
A series of electrical parameters degeneration.Influence to device shows as:Increase over time, the threshold voltage increase of PMOS device
Diminish with leakage current, the influence circuit shows as causing mismatch between transistor in analog circuit, causes in digital circuit
Timing drift, noise margin reduce, or even product failure.
So, this causes that circuit designers must be accomplished by considering NBTI degeneration to circuit performance in Design Stage
Influence, leaves enough design tolerances so that defective goods ensure that circuit function is correct in service life.But larger design is held
Limit necessarily brings the increase of circuit power consumption and chip area.
Therefore, need badly at present a kind of in a kind of simple NBTI degeneration observation circuit preferably gone of chip design.The present invention is proposed
Test device and its method that a kind of MOS device Bias Temperature unstability is degenerated.
The content of the invention
The present invention proposes the test device that a kind of MOS device Bias Temperature unstability is degenerated, including:Circuit under test,
Reference calibrations circuit and detection circuit;The output of the circuit under test and the reference calibrations circuit is connected to the detection simultaneously
Circuit;The inside of the circuit under test sets the first feedback control component and the first Schmitt trigger, the first feedback control
Component processed and the first Schmitt trigger are connected, and first feedback control component is in the first Schmitt trigger
Backfeed loop component to be measured applies stress so that the backfeed loop component occurs Bias Temperature unstability and degenerates
Effect, realizes changing the feedback oscillator of the first Schmitt trigger, and then changes the slow of the first Schmitt trigger
Stagnant voltage, the actual hysteresis voltage signal after the circuit under test output degeneration;The reference calibrations circuit inside sets second
Feedback control component and the second Schmitt trigger, second feedback control component and the second Schmitt trigger connect
Connect;While the first Schmitt trigger is applied in stress, second feedback control component makes described second, and this is close
Special trigger is not applied in stress, and the feedback oscillator of the second Schmitt trigger keeps constant so that described second this is close
The hysteresis voltage of special trigger keeps constant, the reference calibrations circuit output standard hysteresis voltage signal;The detection circuit
By comparing the difference between the measurement actual hysteresis voltage signal and the normative reference hysteresis voltage signal, for reflecting
The Bias Temperature unstability degree of degeneration of the backfeed loop component.
In the test device that the MOS device Bias Temperature unstability proposed by the present invention is degenerated, the detection circuit
It is XOR gate, the input of the XOR gate receives the actual hysteresis voltage signal and the standard hysteresis voltage signal respectively,
When the level between the actual hysteresis voltage signal and the standard hysteresis voltage signal has differences, the XOR gate is defeated
Go out high level signal, by the bias temperature for measuring the pulse width of the high level signal to test the backfeed loop component
Degree unstability degree of degeneration.
In the test device that the MOS device Bias Temperature unstability proposed by the present invention is degenerated, first feedback
Control assembly includes the 3rd PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 4th PMOS, the 5th PMOS, the 5th NMOS
Pipe, the 6th NMOS tube and the 6th PMOS;3rd PMOS is connected with the grid of the 3rd NMOS tube, for receiving the
One control signal;The source ground of the 3rd NMOS tube, the source electrode of the 3rd PMOS is used to receive the first feedback oscillator
Regulation voltage, drain electrode is connected with the drain electrode of the 3rd NMOS tube;The grid of the 4th NMOS tube and the 4th PMOS
It is connected, for receiving the 0th control signal;The source electrode of the 4th PMOS meets power supply, the source electrode of the 4th NMOS tube and institute
The drain electrode connection of the 3rd NMOS tube is stated, drain electrode is connected with the drain electrode of the 4th PMOS and constitutes the first output end and described first
Schmitt trigger is connected;5th PMOS is connected with the grid of the 5th NMOS tube, for receiving the first control letter
Number;The source ground of the 5th NMOS tube, the source electrode of the 5th PMOS is used to receive the second feedback gain adjustment voltage,
Drain electrode is connected with the drain electrode of the 5th NMOS tube;6th NMOS tube is connected with the grid of the 6th PMOS, is used for
Receive the 0th control signal;The source electrode of the 6th PMOS connects power supply, the source electrode and the described 5th of the 6th NMOS tube
The drain electrode connection of NMOS tube, drain electrode is connected with the drain electrode of the 6th PMOS and constitutes the second output end and first Schmitt
Trigger is connected.
In the test device that the MOS device Bias Temperature unstability proposed by the present invention is degenerated, second feedback
Control assembly includes the 9th PMOS, the 9th NMOS tube, the tenth NMOS tube, the tenth PMOS, the 11st PMOS, the 11st
NMOS tube, the 12nd NMOS tube, the 12nd PMOS and not gate;The grid phase of the 9th PMOS and the 9th NMOS tube
Even, for receiving the first control signal;The source ground of the 9th NMOS tube, the source electrode of the 9th PMOS is used to receive
First feedback gain adjustment voltage, drain electrode is connected with the drain electrode of the 9th NMOS tube;The grid of the tenth PMOS passes through
Not gate is connected with the grid of the tenth NMOS tube, for receiving the 0th control signal;The source ground of the tenth PMOS,
The source electrode of the tenth NMOS tube is connected with the drain electrode of the 9th NMOS tube, and drain electrode is connected with the drain electrode of the tenth PMOS
The first output end is constituted to be connected with the second Schmitt trigger;The grid of the 11st NMOS tube by not gate with it is described
The grid of the 11st PMOS is connected, for receiving the first control signal;The source electrode of the 11st NMOS tube connects power supply, described
The source electrode of the 11st PMOS is used to receive the second feedback gain adjustment voltage, and drain electrode connects with the drain electrode of the 11st NMOS tube
Connect;12nd NMOS tube is connected with the grid of the 12nd PMOS, for receiving the 0th control signal;Described tenth
The source electrode of two PMOSs connects power supply, and the source electrode of the 12nd NMOS tube is connected with the drain electrode of the 11st NMOS tube, drain electrode
Connected second output end that constitutes of drain electrode with the 12nd PMOS is connected with the second Schmitt trigger.
The invention allows for the method for testing that a kind of MOS device Bias Temperature unstability is degenerated, comprise the following steps:
Step one:It is to be measured to the first Schmitt trigger inside using the first feedback control component for circuit under test
Backfeed loop component applies stress;Simultaneously for reference calibrations circuit, using the second feedback control component, to second, this is not close
Backfeed loop component inside special trigger applies stress;
Step 2:Backfeed loop component in the first Schmitt trigger will occur bias temperature under stress
Degree unstability is degenerated, so that change the first Schmitt trigger feedback oscillator, and then it is tactile to change first Schmitt
Send out the hysteresis voltage of device, the actual hysteresis voltage signal after the circuit under test output degeneration;The second Schmitt trigger
There is no the degeneration of Bias Temperature unstability, the sluggish electricity of the reference calibrations circuit output standard in internal backfeed loop component
Pressure signal;
Step 3:Using circuit the contrast actual hysteresis voltage signal and the standard hysteresis voltage signal is detected, count
Calculate the pulse width being had differences between the actual hysteresis voltage signal and the standard hysteresis voltage signal;
Step 4:The pulse width is scaled Bias Temperature unstability degree of degeneration.
It is described to have differences in the method for testing that the MOS device Bias Temperature unstability proposed by the present invention is degenerated
Pulse width be the pulse width of XOR gate output, the input of the XOR gate for the actual hysteresis voltage signal with it is described
Standard hysteresis voltage signal.
It is in the method for testing that the MOS device Bias Temperature unstability proposed by the present invention is degenerated, the pulse is wide
Degree is scaled the conversion method of Bias Temperature unstability degree of degeneration:It is described actual sluggish according to pulse width conversion
The knots modification of voltage signal, and reality is determined according to the curve of the degeneration voltage and hysteresis voltage that carry out emulating acquisition to circuit
Degradation values.
The beneficial effects of the present invention are:The present invention can simultaneously realize that Negative Bias Temperature Instability degenerates (NBTI) and just
Bias Temperature unstability is degenerated the test of (PBTI) characteristic, test device of the present invention with circuit structure is simple, test essence
The characteristics of spending high.
Brief description of the drawings
Fig. 1 is the structure chart of the test device that MOS device Bias Temperature unstability of the present invention is degenerated.
Fig. 2 is the line assumption diagram of circuit under test.
Fig. 3 is the line assumption diagram of reference calibrations circuit.
Fig. 4 is the oscillogram of NBTI degeneration test process.
Fig. 5 is the oscillogram of PBTI degradation testing processes.
Fig. 6 be the first Schmitt trigger correspond to different degree of degenerations when curve of output schematic diagram.
Specific embodiment
With reference to specific examples below and accompanying drawing, the present invention is described in further detail.Implement process of the invention,
Condition, experimental technique etc., in addition to the following special content for referring to, are the universal knowledege and common knowledge of this area, this hair
It is bright that content is not particularly limited.
Refering to Fig. 1, the test device that MOS device Bias Temperature unstability of the present invention is degenerated includes circuit under test, reference
Calibration circuit and detection circuit;The output of circuit under test and reference calibrations circuit is connected to detection circuit simultaneously;Circuit under test
Inside sets the first feedback control component and the first Schmitt trigger, the first feedback control component and the first Schmitt trigger
Connection, the first feedback control component applies stress so that anti-to backfeed loop component to be measured in the first Schmitt trigger
It is fed back to road component and Bias Temperature unstability degradation effect occurs, realizes changing the feedback oscillator of the first Schmitt trigger,
And then the hysteresis voltage of the first Schmitt trigger of change, the actual hysteresis voltage signal after circuit under test output degeneration;With reference to
Calibration circuit inside sets the second feedback control component and the second Schmitt trigger, the second feedback control component and second this is close
Special trigger connection;While the first Schmitt trigger is applied in stress, the second feedback control component makes the second Schmitt
Trigger is not applied in stress, and the feedback oscillator of the second Schmitt trigger keeps constant so that the second Schmitt trigger
Hysteresis voltage keeps constant, reference calibrations circuit output standard hysteresis voltage signal;Detection circuit is actual late by comparing measurement
Difference between stagnant voltage signal and normative reference hysteresis voltage signal, for reflect backfeed loop component Bias Temperature not
Stability degree of degeneration.
The line construction to circuit under test, detection circuit and reference calibrations circuit is further elaborated individually below.
(1) line construction of circuit under test
Refering to Fig. 2, circuit under test includes the first Schmitt trigger and the first feedback control component.First Schmitt is triggered
Two backfeed loop components to be measured, specially NMOS feedback oscillators control pipe 26 and PMOS are provided with the backfeed loop of device
Feedback oscillator control pipe 27.First feedback control component is used to adjust NMOS feedback oscillators control pipe 26 and PMOS feedback oscillator controls
The voltage that the grid of tubulation 27 is applied in, is to be applied in answer when the grid of NMOS feedback oscillators control pipe 26 applies vdd voltage
Power, and be to be applied in stress during the grid of PMOS feedback oscillators control pipe 27 applying 0V voltages.
The line construction of (1.1) first Schmitt triggers
First Schmitt trigger includes:First phase inverter, the second phase inverter, NMOS feedback oscillators control pipe 26, first
NMOS feedback transistors 25, PMOS feedback oscillators control pipe 27 and a PMOS feedback transistors 28.NMOS feedback oscillators are controlled
Pipe 26 and PMOS feedback oscillators control pipe 27 are backfeed loop component to be measured.
First phase inverter includes the first PMOS 22 and the first NMOS tube 21, and the source electrode of the first PMOS 22 connects power supply, the
The source ground of one NMOS tube 21, the first PMOS 22 is connected with the grid of the first NMOS tube 21 and constitutes the input of the first phase inverter
End, for receiving input voltage, the first PMOS 22 is connected with the drain electrode of the first NMOS tube 21 and constitutes the output of the first phase inverter
End.
Second phase inverter includes the second PMOS 24 and the second NMOS tube 23, and the source electrode of the second PMOS 24 connects power supply, the
The source ground of two NMOS tubes 23, the second PMOS 24 is connected with the grid of the second NMOS tube 23 and constitutes the input of the second phase inverter
End, the second PMOS 24 is connected with the drain electrode of the second NMOS tube 23 and constitutes the output end of the second phase inverter.Second phase inverter it is defeated
Enter end to be connected with the output end of the first phase inverter, output end is connected with the output end of calibration circuit to be measured.
The grid of NMOS feedback oscillators control pipe 26 is connected with the output of the first feedback control component, drains anti-phase with first
, for being applied in positive bias temperature instability stress, there is the unstable degradation effect of positive bias temperature in the output end connection of device.
The grid of the first NMOS feedback transistors 25 with it is to be measured calibration circuit output end be connected, source ground, drain electrode and
The source electrode connection of NMOS feedback oscillators control pipe 26, the feedback oscillator for reacting NMOS feedback oscillators control pipe 26, output is real
Border hysteresis voltage signal.
The grid of PMOS feedback oscillators control pipe 27 is connected with the output of the first feedback control component, drains anti-phase with first
, for being applied in negative temperature bias instability stress, there is the unstable degradation effect of negative temperature bias in the output end connection of device.
The grid of the first PMOS feedback transistors 28 is connected with the output end of calibration circuit to be measured, and source electrode connects power supply, drain electrode
Source electrode with PMOS feedback oscillators control pipe 27 is connected, the feedback oscillator for reacting PMOS feedback oscillators control pipe 27, output
Actual hysteresis voltage signal.
The control method and line construction of (1.2) first feedback control components
The input of the first feedback control component includes the 0th control signal, the first control signal, the first feedback gain adjustment
Voltage, the second feedback gain adjustment voltage, its output include the first output end and the second output end.First output end is anti-with NMOS
The grid connection of feedforward gain control pipe 26, the second output end is connected with the grid of PMOS feedback oscillators control pipe 27.
First feedback control component includes the 3rd PMOS 29, the 3rd NMOS tube 30, the 4th NMOS tube 31, the 4th PMOS
32nd, the 5th PMOS 33, the 5th NMOS tube 34, the 6th NMOS tube 35 and the 6th PMOS 36.
3rd PMOS 29 is connected with the grid of the 3rd NMOS tube 30, for receiving the first control signal.3rd NMOS tube
30 source ground, the source electrode of the 3rd PMOS 29 is used to receive the first feedback gain adjustment voltage, drain electrode and the 3rd NMOS tube
30 drain electrode connection.4th NMOS tube 31 is connected with the grid of the 4th PMOS 32, for receiving the 0th control signal.4th
The source electrode of PMOS 32 connects power supply, and the source electrode of the 4th NMOS tube 31 is connected with the drain electrode of the 3rd NMOS tube 30, drain electrode and the 4th
Connected first output end that constitutes of the drain electrode of PMOS 32 is connected with the grid of NMOS feedback oscillators control pipe 26.
5th PMOS 33 is connected with the grid of the 5th NMOS tube 34, for receiving the first control signal.5th NMOS tube
34 source ground, the source electrode of the 5th PMOS 33 is used to receive the second feedback gain adjustment voltage, drain electrode and the 5th NMOS tube
34 drain electrode connection.6th NMOS tube 35 is connected with the grid of the 6th PMOS 36, for receiving the 0th control signal.6th
The source electrode of PMOS 36 connects power supply, and the source electrode of the 6th NMOS tube 35 is connected with the drain electrode of the 5th NMOS tube 34, drain electrode and the 6th
Connected second output end that constitutes of the drain electrode of PMOS 36 is connected with the grid of PMOS feedback oscillators control pipe 27.
When the first control signal and the 0th control signal are all low level, the grid of PMOS feedback oscillators control pipe 27 connects
VDD power supplys, the grid of NMOS feedback oscillators control pipe 26 connects VDD power supplys, for applying just to NMOS feedback oscillators control pipe 26
Bias Temperature instability stress.
When the first control signal is low level, and the 0th control signal is high level, PMOS feedback oscillators control pipe 27
Grid connects the second feedback gain adjustment voltage, and the grid of NMOS feedback oscillators control pipe 26 connects the first feedback gain adjustment voltage,
Bias Temperature unstability degeneration journey for testing NMOS feedback oscillators control pipe 26 or NMOS feedback oscillators control pipe 27
Degree.
When the first control signal is high level, and the 0th control signal is low level, PMOS feedback oscillators control pipe 27
Grid disconnects, and the grid of NMOS feedback oscillators control pipe 26 disconnects, for terminating or fixing tentatively test.
When the first control signal and the 0th control signal are all high level, the grid of PMOS feedback oscillators control pipe 27 connects
Ground, the grounded-grid of NMOS feedback oscillators control pipe 26, for applying negative temperature bias not to PMOS feedback oscillators control pipe 26
Stable stress.
(2) line construction of reference calibrations circuit
Refering to Fig. 3, reference calibrations circuit includes the second Schmitt trigger and the second feedback control component.
The line construction of (2.1) second Schmitt triggers
Second Schmitt trigger is identical with the structure of the first Schmitt trigger, and it includes the 3rd phase inverter, the 4th anti-
Phase device, NMOS standard feedbacks gain tube 6, the 8th NMOS feedback transistors 5, PMOS standard feedbacks gain tube 7 and the 7th PMOS are anti-
Feedback transistor 8.NMOS standard feedbacks gain tube 6 and PMOS standard feedbacks gain tube 7 are normal component.
3rd phase inverter includes the 7th PMOS 2 and the 7th NMOS tube 1, and the source electrode of the 7th PMOS 2 connects power supply, the 7th
The source ground of NMOS tube 1, the 7th PMOS 2 is connected with the grid of the 7th NMOS tube 1 and constitutes the input of the 3rd phase inverter, uses
In input voltage is received, the 7th PMOS 2 is connected with the drain electrode of the 7th NMOS tube 1 and constitutes the output end of the 3rd phase inverter.
4th phase inverter includes the 8th PMOS 4 and the 8th NMOS tube 3, and the source electrode of the 8th PMOS 4 connects power supply, the 8th
The source ground of NMOS tube 3, the 8th PMOS 4 is connected with the grid of the 8th NMOS tube 3 and constitutes the input of the 4th phase inverter, the
Eight PMOSs 4 are connected with the drain electrode of the 8th NMOS tube 3 and constitute the output end of the 4th phase inverter.The input of the 4th phase inverter and
The output end connection of three phase inverters, output end is connected with the output end of calibration circuit to be measured.
The grid of NMOS standard feedbacks gain tube 6 is connected with the output of the 7th feedback control component, drains anti-phase with the 3rd
There is no the unstable degradation effect of positive bias temperature in the output end connection of device, NMOS standard feedbacks gain tube 6.
The grid of the 8th NMOS feedback transistors 5 with it is to be measured calibration circuit output end be connected, source ground, drain electrode and
The source electrode connection of NMOS standard feedbacks gain tube 6, the feedback oscillator for reacting NMOS standard feedbacks gain tube 6, outputting standard
Hysteresis voltage signal.
The grid of PMOS standard feedbacks gain tube 7 is connected with the output of the 7th feedback control component, drains anti-phase with the 3rd
There is no the unstable degradation effect of negative temperature bias in the output end connection of device, PMOS standard feedbacks gain tube 7..
The grid of the 7th PMOS feedback transistors 8 be connected with the output end of calibration circuit to be measured, and source electrode connects power supply, drain electrode and
The source electrode connection of PMOS standard feedbacks gain tube 7, the feedback oscillator for reacting PMOS standard feedbacks gain tube 7, outputting standard
Hysteresis voltage signal.
The control method and line construction of (2.2) second feedback control components
The input of the second feedback control component includes the 0th control signal, the first control signal, the first feedback gain adjustment
Voltage, the second feedback gain adjustment voltage, its output include the 3rd output end and the 4th output end.3rd output end is marked with NMOS
The grid connection of quasi- feedback oscillator pipe 6, the 4th output end is connected with the grid of PMOS standard feedbacks gain tube 7.
When the first control signal and the 0th control signal are all low level, the grid of PMOS standard feedbacks gain tube 7 connects
Power supply, the grounded-grid of NMOS standard feedbacks gain tube 6, for making NMOS standard feedbacks gain tube 6 or PMOS standard feedbacks
There is no Bias Temperature unstability degradation effect in gain tube 7.
When the first control signal is low level, and the 0th control signal is high level, the grid of PMOS standard feedbacks gain tube 7
Pole connects the second feedback gain adjustment voltage, and the grid of NMOS standard feedbacks gain tube 6 connects the first feedback gain adjustment voltage, is used for
Outputting standard hysteresis voltage signal.
When the first control signal is high level, and the 0th control signal is low level, the grid of PMOS standard feedbacks gain tube 7
Pole disconnects, and the grid of NMOS standard feedbacks gain tube 6 disconnects, for terminating or fixing tentatively test.
When the first control signal and the 0th control signal are all high level, the grid of PMOS standard feedbacks gain tube 7 connects
Power supply, the grounded-grid of NMOS standard feedbacks gain tube 6, for making NMOS standard feedbacks gain tube 6 or PMOS standard feedbacks
There is no Bias Temperature unstability degradation effect in gain tube 7.
Second feedback control component includes the 9th PMOS 9, the 9th NMOS tube 10, the tenth NMOS tube 11, the tenth PMOS
12nd, the 11st PMOS 13, the 11st NMOS tube 14, the 12nd NMOS tube 15, the 12nd PMOS 16 and not gate.
9th PMOS 9 is connected with the grid of the 9th NMOS tube 10, for receiving the first control signal.9th NMOS tube 10
Source ground, the source electrode of the 9th PMOS 9 is used to receive the first feedback gain adjustment voltage, drain electrode and the 9th NMOS tube 10
Drain electrode connection.The grid of the tenth PMOS 12 is connected by not gate with the grid of the tenth NMOS tube 11, is controlled for receiving the 0th
Signal.The source ground of the tenth PMOS 12, the source electrode of the tenth NMOS tube 11 is connected with the drain electrode of the 9th NMOS tube 10, drain electrode with
Connected first output end that constitutes of the drain electrode of the tenth PMOS 12 is connected with the grid of NMOS feedback oscillators control pipe 6.
The grid of the 11st NMOS tube 14 is connected by not gate with the grid of the 11st PMOS 13, is controlled for receiving first
Signal processed.The source electrode of the 11st NMOS tube 14 connects power supply, and the source electrode of the 11st PMOS 13 is used to receive the second feedback oscillator tune
Economize on electricity pressure, drain electrode is connected with the drain electrode of the 11st NMOS tube 14.The grid phase of the 12nd NMOS tube 15 and the 12nd PMOS 16
Even, for receiving the 0th control signal.The source electrode of the 12nd PMOS 16 connects power supply, the source electrode and the tenth of the 12nd NMOS tube 15
The drain electrode connection of one NMOS tube 14, drain electrode is connected to constitute the second output end and fed back with PMOS with the drain electrode of the 12nd PMOS 16 and increases
The grid connection of beneficial control pipe 7.
Above is the detailed description on test device internal wiring structure of the present invention, the technical scheme is that with this
NMOS feedback oscillators control pipe or PMOS feedback oscillators control pipe in schmitt trigger as backfeed loop component to be measured,
BTI degenerations stress transmission is degenerated into the feedback oscillator of Schmitt trigger, so as to be converted into Schmitt trigger hysteresis voltage
Change.The step of present invention below method of testing and specific implementation process are described further.
The invention allows for the method for testing that a kind of MOS device Bias Temperature unstability is degenerated, comprise the following steps:
Step one:It is to be measured to the first Schmitt trigger inside using the first feedback control component for circuit under test
Backfeed loop component applies stress;Simultaneously for reference calibrations circuit, using the second feedback control component, to second, this is not close
Backfeed loop component inside special trigger applies stress;
Step 2:Backfeed loop component in first Schmitt trigger will occur Bias Temperature not under stress
Stabilization sexual involution, so as to change the first Schmitt trigger feedback oscillator, and then changes the sluggishness electricity of the first Schmitt trigger
Pressure, the actual hysteresis voltage signal after circuit under test output degeneration;Backfeed loop component inside second Schmitt trigger
Generation Bias Temperature unstability is degenerated, reference calibrations circuit output standard hysteresis voltage signal;
Step 3:Using the actual hysteresis voltage signal of circuit contrast and standard hysteresis voltage signal is detected, calculate actual slow
The pulse width being had differences between stagnant voltage signal and standard hysteresis voltage signal;
Step 4:Pulse width is scaled Bias Temperature unstability degree of degeneration.
With reference to the line construction of the invention described above test device, the first Schmitt trigger is biased in the present embodiment
The pattern of temperature instability degeneration stress is divided into four kinds, and NBTI applies stress mode, PBTI and applies stress mode, test pattern
And prohibited mode.The control signal feature list of each pattern is as shown in the following Table 1:
The control signal function of table 1
Referring to upper table 1, in PBTI stress modes (in { CS1, CS0 }=00):5th PMOS 33, the 6th PMOS
36 are opened, and the 5th NMOS tube 34 and the 6th NMOS tube 35 are closed, now node A (i.e. the grid of PMOS feedback oscillators control pipe 27)
Voltage is VDD, and PMOS feedback oscillators control pipe 27 is not in stress and applies the stage;While the 3rd NMOS tube 30, the 4th NMOS tube
31 are closed, and the 3rd PMOS 29 and the 4th PMOS 32 are opened, now node B (grid of NMOS feedback oscillators control pipe 26) electricity
It is VDD to press, and the pipe of NMOS feedback oscillators control pipe 26 is in applying stage of stress.
Test pattern ({ CS1, CS0 }=01):5th PMOS 33, the 6th NMOS tube 35 are opened, the He of the 5th NMOS tube 34
6th PMOS 36 is closed, and now node A voltage is the second outside feedback gain adjustment voltage Vbiasp, PMOS feedback oscillator
Control pipe 27 will be in test pattern;The 3rd PMOS 29, the 4th NMOS tube 31 are opened simultaneously, the 3rd NMOS tube 30 and the 4th
PMOS 32 is closed, and now node B voltage is managed for the first feedback gain adjustment voltage Vbiasn, NMOS feedback oscillator control pipe 26
In test pattern.That is, NBTI and PBTI tests belong to a pattern together.
Prohibited mode ({ CS1, CS0 }=10):Forbid this kind of control signal occur in whole work process.
NBTI stress modes ({ CS1, CS0 }=11):5th NMOS tube 34, the 6th NMOS tube 35 are opened, the 5th PMOS
33 and the 6th PMOS 36 close, now node A voltage be GND, PMOS feedback oscillators control pipe 27 be in NBTI stress applying
Stage;The 3rd PMOS 29, the 4th PMOS 32 are closed simultaneously, and the 3rd NMOS tube 30 and the 4th NMOS tube 31 are opened, this time
Point B voltages are GND, do not apply stress to the pipe of NMOS feedback oscillators control pipe 26.
The quasi- circuit of reference member includes the second Schmitt trigger and the second feedback control component, the second Schmitt trigger
Line construction it is identical with the line construction of the first Schmitt trigger.The same of stress is applied in the first Schmitt trigger
When, the second Schmitt trigger is not applied in stress, and the standard hysteresis voltage signal of its output is for actual sluggish as comparing
The foundation of voltage signal.Correspondingly, reference calibrations circuit has three kinds of mode of operations:Test pattern, do not receive stress mode and taboo
Only pattern.Its control signal feature list is as shown in the following Table 2:
The reference circuit control signal feature list of table 2
Referring to Fig. 2, not by stress mode under, { CS1, CS0 }=00:11st PMOS 13, the 12nd PMOS 16 are opened
Open, the 11st NMOS tube 14 and the 12nd NMOS tube 15 are closed, now node C (i.e. the grid of PMOS standard feedbacks gain tube 7)
Voltage is VDD, and PMOS standard feedbacks gain tube 7 is not in stress and applies the stage;While the 9th NMOS tube 10, the tenth NMOS tube 11
Close, the 9th PMOS 9 and the tenth PMOS 12 are opened, now node D (i.e. the grid of NMOS standard feedbacks gain tube 6) voltage
It is GND, the pipe of NMOS standard feedbacks gain tube 6 is in and does not apply stress state.
Under test pattern, { CS1, CS0 }=01:11st PMOS 13, the 12nd NMOS tube 15 are opened, the 11st NMOS
The PMOS 16 of pipe 14 and the 12nd is closed, and now node C voltage is external regulating voltage Vbiasp, PMOS standard feedback gain tube
7 will be in test pattern;The 9th PMOS 9, the tenth NMOS tube 11 are opened simultaneously, and the 9th NMOS tube 10 and the tenth PMOS 12 are closed
Close, now node D voltages are Vbiasn, the pipe of NMOS standard feedbacks gain tube 6 is in test pattern.That is, NBTI and PBTI is tested
Belong to a pattern together.
Under prohibited mode, { CS1, CS0 }=10:Forbid this kind of control signal occur in whole work process.
By under stress mode, { CS1, CS0 }=11:11st NMOS tube 14, the 12nd NMOS tube 15 are opened, and the 11st
The PMOS 16 of PMOS 13 and the 12nd is closed, and now node C voltage is VDD, and PMOS standard feedbacks gain tube 7 is in non-NBTI
Stress applies the stage;The 9th PMOS 9, the tenth PMOS 12 are closed simultaneously, and the 9th NMOS tube 10 and the tenth NMOS tube 11 are opened,
Now node D voltages are GND, and the pipe of NMOS standard feedbacks gain tube 6 is in and does not apply stage of stress.As can be seen here, no matter
Why CS1CS0 is worth, NMOS standard feedbacks gain tube 6 and PMOS standard feedbacks gain tube 7 be not in by stress state, because
This can be used as the reference of circuit to be tested.
Whole test process includes first carrying out stress applying, is then tested again.The waveform of its test process such as Fig. 4 and
Shown in Fig. 5,
NBTI degeneration test process:
{ CS1, CS0 } is arranged to 11, stress is applied to the pipe of PMOS standard feedbacks gain tube 7, { CS1, CS0 }=00 is stopped
Only apply stress, condition is applied so repeatedly until terminating according to stress.
At the end of stress applying process, { CS1, CS0 } is arranged to 01, while Vin starts to be gradually decreased to from VDD
GND, fall off rate is by outside source control.Vout1 is the reference calibrations circuit output for not applying stress, and Vout2 is applying
Overstress testing circuit output.Have a delay relative to Vout1 because NBTI degeneration can cause Vout2, thus Vout1 and
Vout2 by can produce a high level pulse after XOR gate, pulsewidths representative device performance degeneration degree.
PBTI degradation testing processes:
{ CS1, CS0 } is arranged to 00, stress is applied to the pipe of NMOS standard feedbacks gain tube 6, { CS1, CS0 }=11 are stopped
Only apply stress.Apply condition so repeatedly until stress applies to terminate according to stress.
At the end of stress applies, { CS1, CS0 } is arranged to 01, while Vin starts to gradually rise to VDD from GND, on
The time of liter is by external control.Vout1 is the reference calibrations circuit output for not applying stress, and Vout2 is electric to apply overstress testing
Road exports.There is a delay relative to Vout1 because PBTI degenerations can cause Vout2.Vout1 and Vout2 will by XOR gate
Delay-time difference is converted into a high level pulse, pulsewidths representative device performance degeneration degree.
The specific control mode of the method for testing that MOS device Bias Temperature unstability of the present invention set forth above is degenerated,
Below in conjunction with by taking NBTI degeneration test process as an example, specific explanations illustrate the process and principle of method of testing.PBTI degradation testings
Process and its principle are similar with NBTI degeneration test process.
By taking NBTI degeneration test process as an example, after PMOS feedback oscillators control pipe 27 is applied in stress, PMOS feedbacks
The threshold voltage of gain control pipe 27 can increase with stress time, because PMOS feedback oscillators control pipe 27 is located at test electricity
(referring to the arrow of Fig. 2) on the backfeed loop of road Schmitt trigger, therefore PMOS feedback oscillators control caused by NBTI degeneration
The change of the threshold voltage of pipe 27 can cause the first Schmitt trigger feedback oscillator to change, so as to cause the first Schmitt trigger
Hysteresis voltage change.
When circuit under test and reference calibrations circuit are input into identical Vin signal (triangular waves) simultaneously, due to circuit under test
In the hysteresis voltage of the first Schmitt trigger change, cause the actual hysteresis voltage signal of output relative to referring to school
The rising edge of the standard hysteresis voltage signal of the output of quasi- circuit shifts to an earlier date.Finally compare two output waveforms using XOR gate, can
Output pulse is obtained, this pulse width is Timing Advance of the circuit under test relative to reference calibrations circuit rising edge, so should
Pulse width can react the degree of degeneration of PMOS feedback oscillators control pipe 27.
When PMOS feedback oscillators control pipe 27 is degenerated (threshold voltage changes), PMOS feedback oscillators are equivalent to
The grid effective voltage of control pipe 27 changes.Referring to Fig. 6, for same input Vin, the first Schmitt trigger it is defeated
Going out curve (i.e. actual hysteresis voltage signal) can shift.
Assuming that Vbiasp is a fixed value, ignores the 5th PMOS 33 and the voltage drop caused by the 6th NMOS tube 35 (can
The transmission gate constituted with complementary cmos pipe substitutes single metal-oxide-semiconductor transmission gate), do not add on the grid of PMOS feedback oscillators control pipe 27 and occur
Voltage during degeneration is Vbiasp, and the overdrive voltage of PMOS feedback oscillators control pipe 27 is Vbiasp-Vth0, and wherein Vth0 is
Threshold voltage when PMOS feedback oscillators control pipe 27 is degenerated, is a constant.Assuming that PMOS feedback oscillators control pipe 27
There is the degeneration of △ Vth, then effective overdrive voltage of PMOS feedback oscillators control pipe 27 is Vbiasp-Vth0- △ Vth.No
With overdrive voltage can cause the change of hysteresis voltage in as above figure, reaction is input Vin and defeated to hysteresis voltage in figure 6 surely
The corresponding longitudinal axis voltage of intersection point for going out.Be would know that by circuit simulation and PMOS feedback oscillators control pipe 27 degenerate (threshold voltage changes
Become) with the relation curve of pulse width.In actual test, the relation curve that can be obtained by emulation after pulse width is obtained anti-
To the degradation values for deriving threshold voltage.
Protection content of the invention is not limited to above example.Under the spirit and scope without departing substantially from inventive concept, this
Art personnel it is conceivable that change and advantage be all included in the present invention, and with appending claims be protect
Shield scope.
Claims (7)
1. the test device that a kind of MOS device Bias Temperature unstability is degenerated, it is characterised in that including:Circuit under test, reference
Calibration circuit and detection circuit;The output of the circuit under test and the reference calibrations circuit is connected to the detection electricity simultaneously
Road;
The inside of the circuit under test sets the first feedback control component and the first Schmitt trigger, first feedback control
Component and the first Schmitt trigger are connected, and first feedback control component in the first Schmitt trigger to treating
The backfeed loop component of survey applies stress so that the backfeed loop component occurs Bias Temperature unstability degeneration effect
Should, realize changing the feedback oscillator of the first Schmitt trigger, and then change the sluggishness of the first Schmitt trigger
Voltage, the actual hysteresis voltage signal after the circuit under test output degeneration;
The reference calibrations circuit inside sets the second feedback control component and the second Schmitt trigger, the second feedback control
Component processed and the second Schmitt trigger are connected;It is described while the first Schmitt trigger is applied in stress
Second feedback control component makes the second Schmitt trigger not be applied in stress, the feedback of the second Schmitt trigger
Gain keeps constant so that the hysteresis voltage of the second Schmitt trigger keeps constant, the reference calibrations circuit output
Standard hysteresis voltage signal;
The detection circuit by compare the measurement actual hysteresis voltage signal and the normative reference hysteresis voltage signal it
Between difference, the Bias Temperature unstability degree of degeneration for reflecting the backfeed loop component.
2. the test device that MOS device Bias Temperature unstability as claimed in claim 1 is degenerated, it is characterised in that described
Detection circuit is XOR gate, and the input of the XOR gate receives the actual hysteresis voltage signal with the sluggish electricity of the standard respectively
Pressure signal, it is described when the level between the actual hysteresis voltage signal and the standard hysteresis voltage signal has differences
XOR gate exports high level signal, and the backfeed loop component is tested by measuring the pulse width of the high level signal
Bias Temperature unstability degree of degeneration.
3. the test device that MOS device Bias Temperature unstability as claimed in claim 1 is degenerated, it is characterised in that described
First feedback control component includes the 3rd PMOS (29), the 3rd NMOS tube (30), the 4th NMOS tube (31), the 4th PMOS
(32), the 5th PMOS (33), the 5th NMOS tube (34), the 6th NMOS tube (35) and the 6th PMOS (36);
NMOS feedback oscillators control pipe (26) are provided with the backfeed loop of the first Schmitt trigger and PMOS feedbacks increase
Beneficial control pipe (27);
3rd PMOS (29) is connected with the grid of the 3rd NMOS tube (30), for receiving the first control signal;Institute
The source ground of the 3rd NMOS tube (30) is stated, the source electrode of the 3rd PMOS (29) is used to receive the first feedback gain adjustment electricity
Pressure, the drain electrode of the 3rd PMOS (29) is connected with the drain electrode of the 3rd NMOS tube (30);4th NMOS tube (31)
Grid with the 4th PMOS (32) is connected, for receiving the 0th control signal;The source electrode of the 4th PMOS (32)
Power supply is connect, the source electrode of the 4th NMOS tube (31) is connected with the drain electrode of the 3rd NMOS tube (30), the 4th NMOS tube
(31) drain electrode be connected with the drain electrode of the 4th PMOS (32) composition the first output end controlled with the NMOS feedback oscillators
Manage the grid connection of (26);
5th PMOS (33) is connected with the grid of the 5th NMOS tube (34), for receiving the first control signal;Institute
The source ground of the 5th NMOS tube (34) is stated, the source electrode of the 5th PMOS (33) is used to receive the second feedback gain adjustment electricity
Pressure, the drain electrode of the 5th PMOS (33) is connected with the drain electrode of the 5th NMOS tube (34);6th NMOS tube (35)
Grid with the 6th PMOS (36) is connected, for receiving the 0th control signal;The source electrode of the 6th PMOS (36)
Power supply is connect, the source electrode of the 6th NMOS tube (35) is connected with the drain electrode of the 5th NMOS tube (34), the 6th NMOS tube
(35) drain electrode be connected with the drain electrode of the 6th PMOS (36) composition the second output end controlled with the PMOS feedback oscillators
Manage the grid connection of (27).
4. the test device that MOS device Bias Temperature unstability as claimed in claim 1 is degenerated, it is characterised in that described
Second feedback control component includes the 9th PMOS (9), the 9th NMOS tube (10), the tenth NMOS tube (11), the tenth PMOS
(12), the 11st PMOS (13), the 11st NMOS tube (14), the 12nd NMOS tube (15), the 12nd PMOS (16) and non-
Door;
The second Schmitt trigger includes NMOS standard feedbacks gain tube (6), PMOS standard feedbacks gain tube (7);
9th PMOS (9) is connected with the grid of the 9th NMOS tube (10), for receiving the first control signal;It is described
The source ground of the 9th NMOS tube (10), the source electrode of the 9th PMOS (9) is used to receive the first feedback gain adjustment voltage,
The drain electrode of the 9th PMOS (9) is connected with the drain electrode of the 9th NMOS tube (10);The grid of the tenth PMOS (12)
Pole is connected by not gate with the grid of the tenth NMOS tube (11), for receiving the 0th control signal;Tenth PMOS
(12) source ground, the source electrode of the tenth NMOS tube (11) is connected with the drain electrode of the 9th NMOS tube (10), and described
The drain electrode of ten NMOS tubes (11) is connected with the drain electrode of the tenth PMOS (12) and constitutes the 3rd output end and the NMOS standards
The grid connection of feedback oscillator pipe (6);
The grid of the 11st NMOS tube (14) is connected by not gate with the grid of the 11st PMOS (13), for connecing
Receive the first control signal;The source electrode of the 11st NMOS tube (14) connects power supply, and the source electrode of the 11st PMOS (13) is used
In the second feedback gain adjustment voltage of reception, drain electrode and the 11st NMOS tube (14) of the 11st PMOS (13)
Drain electrode connection;12nd NMOS tube (15) is connected with the grid of the 12nd PMOS (16), is controlled for receiving the 0th
Signal processed;The source electrode of the 12nd PMOS (16) connects power supply, the source electrode and the described tenth of the 12nd NMOS tube (15)
The drain electrode connection of one NMOS tube (14), the drain electrode of the 12nd NMOS tube (15) and the drain electrode of the 12nd PMOS (16)
The 4th output end of the composition that is connected is connected with the grid of the PMOS standard feedbacks gain tube (7).
5. the method for testing that a kind of MOS device Bias Temperature unstability is degenerated, it is characterised in that comprise the following steps:
Step one:For circuit under test, using the first feedback control component feedback to be measured to the first Schmitt trigger inside
Loop component applies stress;Simultaneously for reference calibrations circuit, the second Schmitt is not touched using the second feedback control component
Backfeed loop component inside hair device applies stress;
Step 2:Backfeed loop component in the first Schmitt trigger will occur Bias Temperature not under stress
Stabilization sexual involution, so as to change the first Schmitt trigger feedback oscillator, and then changes the first Schmitt trigger
Hysteresis voltage, circuit under test output degenerate after actual hysteresis voltage signal;Inside the second Schmitt trigger
Backfeed loop component there is no the degeneration of Bias Temperature unstability, reference calibrations circuit output standard hysteresis voltage letter
Number;
Step 3:Using circuit the contrast actual hysteresis voltage signal and the standard hysteresis voltage signal is detected, institute is calculated
State the pulse width being had differences between actual hysteresis voltage signal and the standard hysteresis voltage signal;
Step 4:The pulse width is scaled Bias Temperature unstability degree of degeneration.
6. the method for testing that MOS device Bias Temperature unstability as claimed in claim 5 is degenerated, it is characterised in that described
The pulse width having differences is the pulse width of XOR gate output, and the input of the XOR gate is the actual hysteresis voltage letter
Number with the standard hysteresis voltage signal.
7. the method for testing that MOS device Bias Temperature unstability as claimed in claim 5 is degenerated, it is characterised in that by institute
State pulse width and be scaled the conversion method of Bias Temperature unstability degree of degeneration and be:According to pulse width conversion
The knots modification of actual hysteresis voltage signal, and it is true with the curve of hysteresis voltage according to the degeneration voltage for circuit emulate acquisition
Fixed actual degradation values.
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CN113381739A (en) * | 2021-06-25 | 2021-09-10 | 上海威固信息技术股份有限公司 | Schmitt trigger with adjustable positive and negative threshold voltages |
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