CN104483611A - Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device - Google Patents
Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device Download PDFInfo
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- CN104483611A CN104483611A CN201410681403.7A CN201410681403A CN104483611A CN 104483611 A CN104483611 A CN 104483611A CN 201410681403 A CN201410681403 A CN 201410681403A CN 104483611 A CN104483611 A CN 104483611A
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Abstract
The invention discloses a device for testing bias temperature instability degrading of a MOS (metal oxide semiconductor) device. The device comprises a to-be-tested circuit, a reference calibration circuit and a detection circuit, wherein the output ends of the to-be-tested circuit and the reference calibration circuit are simultaneously connected with the detection circuit, a first feedback control assembly and a first Schmitt trigger are arranged in the to-be-tested circuit, the first feedback control assembly is used for applying stress on to-be-tested feedback loop components in the first Schmitt trigger so as to generate degrading, the to-be-tested circuit is used for outputting degraded actual hysteresis voltage signals, the reference calibration circuit is used for outputting standard hysteresis voltage signals, and the detection circuit is used for comparing and measuring the difference between the actual hysteresis voltage signals and the reference standard hysteresis voltage signals, so as to test the degrading degree of the feedback loop components. The device has the characteristics that the NBTI (negative bias temperature instability) and PBTI (positive bias temperature instability) properties can be tested, the circuit structure is simple, and the testing accuracy is high. The invention discloses a method for testing the bias temperature instability degrading of the MOS device.
Description
Technical field
The invention belongs to and belong to semiconductor device reliability technical field, particularly relate to the proving installation that a kind of MOS device Bias Temperature instability is degenerated.
Background technology
Along with semiconductor process techniques enters deep sub-micron era, Negative Bias Temperature Instability (NBTI) becomes one of principal element affecting device performance degeneration and life-span.NBTI effect refers to the degeneration of a series of electrical parameters at high temperature caused PMOS device applying minus gate voltage.The impact of device is shown as: along with the time increases, the threshold voltage of PMOS device increases and leakage current diminishes, the impact of circuit is shown as in mimic channel, causes mismatch between transistor, in digital circuit, cause timing drift, noise margin reduces, even product failure.
So this makes circuit designers must just need to consider that NBTI degenerates impact on circuit performance at Design Stage, leave enough design tolerances defective goods are ensured within serviceable life circuit function is correct.But larger design tolerances must bring the increase of circuit power consumption and chip area.
Therefore, need badly at present a kind of at a kind of NBTI degeneration observation circuit simply should gone of chip design.The present invention proposes proving installation and the method thereof of the degeneration of a kind of MOS device Bias Temperature instability.
Summary of the invention
The present invention proposes the proving installation that a kind of MOS device Bias Temperature instability is degenerated, comprising: circuit under test, reference calibrations circuit and testing circuit, the output of described circuit under test and described reference calibrations circuit is connected to described testing circuit simultaneously, the inside of described circuit under test arranges the first feedback control component and first this schmitt trigger, described first feedback control component is connected with described first this schmitt trigger, described first feedback control component applies stress to backfeed loop components and parts to be measured in described first this schmitt trigger thus makes described backfeed loop components and parts generation Bias Temperature instability degradation effect, realize the feedback gain changing described first this schmitt trigger, and then change the hysteresis voltage of described first this schmitt trigger, described circuit under test exports the actual hysteresis voltage signal after degenerating, described reference calibrations inside circuit arranges the second feedback control component and second this schmitt trigger, and described second feedback control component is connected with described second this schmitt trigger, while described first this schmitt trigger is applied in stress, described second feedback control component makes described second this schmitt trigger not be applied in stress, the feedback gain of described second this schmitt trigger remains unchanged thus the hysteresis voltage of described second this schmitt trigger is remained unchanged, described reference calibrations circuit outputting standard hysteresis voltage signal, described testing circuit by comparing and measuring the difference between described actual hysteresis voltage signal and described normative reference hysteresis voltage signal, for reflecting the Bias Temperature instability degree of degeneration of described backfeed loop components and parts.
In the proving installation that the described MOS device Bias Temperature instability that the present invention proposes is degenerated, described testing circuit is XOR gate, the input of described XOR gate receives described actual hysteresis voltage signal and described standard hysteresis voltage signal respectively, when level between described actual hysteresis voltage signal and described standard hysteresis voltage signal there are differences, described XOR gate exports high level signal, by measuring the pulse width of described high level signal to test the Bias Temperature instability degree of degeneration of described backfeed loop components and parts.
In the proving installation that the described MOS device Bias Temperature instability that the present invention proposes is degenerated, described first feedback control component comprises the 3rd PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 4th PMOS, the 5th PMOS, the 5th NMOS tube, the 6th NMOS tube and the 6th PMOS; Described 3rd PMOS is connected with the grid of described 3rd NMOS tube, for receiving the first control signal; The source ground of described 3rd NMOS tube, the source electrode of described 3rd PMOS is for receiving the first feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 3rd NMOS tube; Described 4th NMOS tube is connected with the grid of described 4th PMOS, for receiving the 0th control signal; The source electrode of described 4th PMOS connects power supply, and the source electrode of described 4th NMOS tube is connected with the drain electrode of described 3rd NMOS tube, and formation first output terminal that to be connected with the drain electrode of described 4th PMOS of draining is connected with described first this schmitt trigger; Described 5th PMOS is connected with the grid of described 5th NMOS tube, for receiving the first control signal; The source ground of described 5th NMOS tube, the source electrode of described 5th PMOS is for receiving the second feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 5th NMOS tube; Described 6th NMOS tube is connected with the grid of described 6th PMOS, for receiving the 0th control signal; The source electrode of described 6th PMOS connects power supply, and the source electrode of described 6th NMOS tube is connected with the drain electrode of described 5th NMOS tube, and formation second output terminal that to be connected with the drain electrode of described 6th PMOS of draining is connected with described first this schmitt trigger.
In the proving installation that the described MOS device Bias Temperature instability that the present invention proposes is degenerated, described second feedback control component comprises the 9th PMOS, the 9th NMOS tube, the tenth NMOS tube, the tenth PMOS, the 11 PMOS, the 11 NMOS tube, the 12 NMOS tube, the 12 PMOS and not gate; Described 9th PMOS is connected with the grid of described 9th NMOS tube, for receiving the first control signal; The source ground of described 9th NMOS tube, the source electrode of described 9th PMOS is for receiving the first feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 9th NMOS tube; The grid of described tenth PMOS is connected, for receiving the 0th control signal by the grid of not gate with described tenth NMOS tube; The source ground of described tenth PMOS, the source electrode of described tenth NMOS tube is connected with the drain electrode of described 9th NMOS tube, and formation first output terminal that to be connected with the drain electrode of described tenth PMOS of draining is connected with described second this schmitt trigger; The grid of described 11 NMOS tube is connected by the grid of not gate with described 11 PMOS, for receiving the first control signal; The source electrode of described 11 NMOS tube connects power supply, and the source electrode of described 11 PMOS is for receiving the second feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 11 NMOS tube; Described 12 NMOS tube is connected with the grid of described 12 PMOS, for receiving the 0th control signal; The source electrode of described 12 PMOS connects power supply, and the source electrode of described 12 NMOS tube is connected with the drain electrode of described 11 NMOS tube, and formation second output terminal that to be connected with the drain electrode of described 12 PMOS of draining is connected with described second this schmitt trigger.
The invention allows for the method for testing that a kind of MOS device Bias Temperature instability is degenerated, comprise the steps:
Step one: for circuit under test, the backfeed loop components and parts utilizing the first feedback control component inner to be measured to first this schmitt trigger apply stress; Simultaneously for reference calibrations circuit, the second feedback control component is utilized not apply stress to the backfeed loop components and parts of second this schmitt trigger inside;
Step 2: the backfeed loop components and parts in described first this schmitt trigger Bias Temperature instability will occur under effect of stress and degenerate, thus change described first this schmitt trigger feedback gain, and then changing the hysteresis voltage of described first this schmitt trigger, described circuit under test exports the actual hysteresis voltage signal after degenerating; There is not Bias Temperature instability and degenerate in the backfeed loop components and parts of described second this schmitt trigger inside, described reference calibrations circuit outputting standard hysteresis voltage signal;
Step 3: utilize testing circuit to contrast described actual hysteresis voltage signal and described standard hysteresis voltage signal, calculate the pulse width that there are differences between described actual hysteresis voltage signal and described standard hysteresis voltage signal;
Step 4: described pulse width is scaled Bias Temperature instability degree of degeneration.
In the method for testing that the described MOS device Bias Temperature instability that the present invention proposes is degenerated, the described pulse width that there are differences be XOR gate export pulse width, described XOR gate be input as described actual hysteresis voltage signal and described standard hysteresis voltage signal.
In the method for testing that the described MOS device Bias Temperature instability that the present invention proposes is degenerated, the conversion method described pulse width being scaled Bias Temperature instability degree of degeneration is: the knots modification of the described actual hysteresis voltage signal that converts according to described pulse width, and determines actual degradation values according to the curve carrying out emulating degeneration voltage and the hysteresis voltage obtained to circuit.
Beneficial effect of the present invention is: the present invention can realize degenerate (NBTI) and positive bias temperature instability of Negative Bias Temperature Instability simultaneously and to degenerate the test of (PBTI) characteristic, proving installation of the present invention have the advantages that circuit structure is simple, measuring accuracy is high.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the proving installation that MOS device Bias Temperature instability of the present invention is degenerated.
Fig. 2 is the line assumption diagram of circuit under test.
Fig. 3 is the line assumption diagram of reference calibrations circuit.
Fig. 4 is the oscillogram of NBTI degradation testing process.
Fig. 5 is the oscillogram of PBTI degradation testing process.
Fig. 6 is that first this schmitt trigger is corresponding to curve of output schematic diagram during different degree of degeneration.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the following content mentioned specially, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
Consult Fig. 1, the proving installation that MOS device Bias Temperature instability of the present invention is degenerated comprises circuit under test, reference calibrations circuit and testing circuit; The output of circuit under test and reference calibrations circuit is connected to testing circuit simultaneously; The inside of circuit under test arranges the first feedback control component and first this schmitt trigger, first feedback control component is connected with first this schmitt trigger, first feedback control component applies stress to backfeed loop components and parts to be measured in first this schmitt trigger thus makes backfeed loop components and parts generation Bias Temperature instability degradation effect, realize the feedback gain of this schmitt trigger of change first, and then changing the hysteresis voltage of first this schmitt trigger, circuit under test exports the actual hysteresis voltage signal after degenerating; Reference calibrations inside circuit arranges the second feedback control component and second this schmitt trigger, and the second feedback control component is connected with second this schmitt trigger; While first this schmitt trigger is applied in stress, second feedback control component makes second this schmitt trigger not be applied in stress, the feedback gain of second this schmitt trigger remains unchanged thus the hysteresis voltage of second this schmitt trigger is remained unchanged, reference calibrations circuit outputting standard hysteresis voltage signal; Testing circuit by comparing and measuring the difference between actual hysteresis voltage signal and normative reference hysteresis voltage signal, for reflecting the Bias Temperature instability degree of degeneration of backfeed loop components and parts.
Below respectively the line construction of circuit under test, testing circuit and reference calibrations circuit is further elaborated.
(1) line construction of circuit under test
Consult Fig. 2, circuit under test comprises first this schmitt trigger and the first feedback control component.Be provided with two backfeed loop components and parts to be measured in the backfeed loop of first this schmitt trigger, be specially NMOS feedback gain control tube 26 and PMOS feedback gain control tube 27.The voltage that first feedback control component is applied in for regulating the grid of NMOS feedback gain control tube 26 and PMOS feedback gain control tube 27, for being applied in stress when the grid of NMOS feedback gain control tube 26 applies vdd voltage, and for being applied in stress when the grid of PMOS feedback gain control tube 27 applies 0V voltage.
The line construction of (1.1) first these schmitt triggers
First this schmitt trigger comprises: the first phase inverter, the second phase inverter, NMOS feedback gain control tube the 26, the one NMOS feedback transistor 25, PMOS feedback gain control tube 27 and a PMOS feedback transistor 28.NMOS feedback gain control tube 26 and PMOS feedback gain control tube 27 are backfeed loop components and parts to be measured.
First phase inverter comprises the first PMOS 22 and the first NMOS tube 21, the source electrode of the first PMOS 22 connects power supply, the source ground of the first NMOS tube 21, first PMOS 22 is connected with the grid of the first NMOS tube 21 input end of formation first phase inverter, for receiving input voltage, the first PMOS 22 is connected with the drain electrode of the first NMOS tube 21 output terminal of formation first phase inverter.
Second phase inverter comprises the second PMOS 24 and the second NMOS tube 23, the source electrode of the second PMOS 24 connects power supply, the source ground of the second NMOS tube 23, second PMOS 24 is connected with the grid of the second NMOS tube 23 input end of formation second phase inverter, and the second PMOS 24 is connected with the drain electrode of the second NMOS tube 23 output terminal of formation second phase inverter.The input end of the second phase inverter is connected with the output terminal of the first phase inverter, and output terminal is connected with the output terminal of calibration circuit to be measured.
The grid of NMOS feedback gain control tube 26 is connected with the output of the first feedback control component, and drain electrode is connected with the output terminal of the first phase inverter, for being applied in positive bias temperature instability stress, the unstable degradation effect of positive bias temperature occurs.
The grid of the one NMOS feedback transistor 25 is connected with the output terminal of calibration circuit to be measured, source ground, drain electrode is connected with the source electrode of NMOS feedback gain control tube 26, for reacting the feedback gain of NMOS feedback gain control tube 26, exports actual hysteresis voltage signal.
The grid of PMOS feedback gain control tube 27 is connected with the output of the first feedback control component, and drain electrode is connected with the output terminal of the first phase inverter, for being applied in negative temperature bias instability stress, the unstable degradation effect of negative temperature bias occurs.
The grid of the one PMOS feedback transistor 28 is connected with the output terminal of calibration circuit to be measured, source electrode connects power supply, drain electrode is connected with the source electrode of PMOS feedback gain control tube 27, for reacting the feedback gain of PMOS feedback gain control tube 27, exports actual hysteresis voltage signal.
The control method of (1.2) first feedback control component and line construction
The input of the first feedback control component comprises the 0th control signal, the first control signal, the first feedback gain adjustment voltage, the second feedback gain adjustment voltage, and its output comprises the first output terminal and the second output terminal.First output terminal is connected with the grid of NMOS feedback gain control tube 26, and the second output terminal is connected with the grid of PMOS feedback gain control tube 27.
First feedback control component comprises the 3rd PMOS 29, the 3rd NMOS tube 30, the 4th NMOS tube 31, the 4th PMOS 32, the 5th PMOS 33, the 5th NMOS tube 34, the 6th NMOS tube 35 and the 6th PMOS 36.
3rd PMOS 29 is connected with the grid of the 3rd NMOS tube 30, for receiving the first control signal.The source ground of the 3rd NMOS tube 30, the source electrode of the 3rd PMOS 29 is for receiving the first feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of the 3rd NMOS tube 30.4th NMOS tube 31 is connected with the grid of the 4th PMOS 32, for receiving the 0th control signal.The source electrode of the 4th PMOS 32 connects power supply, and the source electrode of the 4th NMOS tube 31 is connected with the drain electrode of the 3rd NMOS tube 30, and formation first output terminal that to be connected with the drain electrode of the 4th PMOS 32 of draining is connected with the grid of NMOS feedback gain control tube 26.
5th PMOS 33 is connected with the grid of the 5th NMOS tube 34, for receiving the first control signal.The source ground of the 5th NMOS tube 34, the source electrode of the 5th PMOS 33 is for receiving the second feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of the 5th NMOS tube 34.6th NMOS tube 35 is connected with the grid of the 6th PMOS 36, for receiving the 0th control signal.The source electrode of the 6th PMOS 36 connects power supply, and the source electrode of the 6th NMOS tube 35 is connected with the drain electrode of the 5th NMOS tube 34, and formation second output terminal that to be connected with the drain electrode of the 6th PMOS 36 of draining is connected with the grid of PMOS feedback gain control tube 27.
When the first control signal and the 0th control signal are all low level, the grid of PMOS feedback gain control tube 27 connects VDD power supply, the grid of NMOS feedback gain control tube 26 connects VDD power supply, for applying positive bias temperature instability stress to NMOS feedback gain control tube 26.
When the first control signal is low level, when 0th control signal is high level, the grid of PMOS feedback gain control tube 27 connects the second feedback gain adjustment voltage, the grid of NMOS feedback gain control tube 26 connects the first feedback gain adjustment voltage, for testing the Bias Temperature instability degree of degeneration of NMOS feedback gain control tube 26 or NMOS feedback gain control tube 27.
When the first control signal is high level, when the 0th control signal is low level, the grid of PMOS feedback gain control tube 27 disconnects, and the grid of NMOS feedback gain control tube 26 disconnects, for terminating or tentative test.
When the first control signal and the 0th control signal are all high level, the grounded-grid of PMOS feedback gain control tube 27, the grounded-grid of NMOS feedback gain control tube 26, for applying negative temperature bias instability stress to PMOS feedback gain control tube 26.
(2) line construction of reference calibrations circuit
Consult Fig. 3, reference calibrations circuit comprises second this schmitt trigger and the second feedback control component.
The line construction of (2.1) second these schmitt triggers
Second this schmitt trigger is identical with the structure of first this schmitt trigger, and it comprises the 3rd phase inverter, the 4th phase inverter, NMOS standard feedback gain tube the 6, the 8th NMOS feedback transistor 5, PMOS standard feedback gain tube 7 and the 7th PMOS feedback transistor 8.NMOS standard feedback gain tube 6 and PMOS standard feedback gain tube 7 are normal component.
3rd phase inverter comprises the 7th PMOS 2 and the 7th NMOS tube 1, the source electrode of the 7th PMOS 2 connects power supply, the source ground of the 7th NMOS tube 1,7th PMOS 2 is connected with the grid of the 7th NMOS tube 1 input end of formation the 3rd phase inverter, for receiving input voltage, the 7th PMOS 2 is connected with the drain electrode of the 7th NMOS tube 1 output terminal of formation the 3rd phase inverter.
4th phase inverter comprises the 8th PMOS 4 and the 8th NMOS tube 3, the source electrode of the 8th PMOS 4 connects power supply, the source ground of the 8th NMOS tube 3,8th PMOS 4 is connected with the grid of the 8th NMOS tube 3 input end of formation the 4th phase inverter, and the 8th PMOS 4 is connected with the drain electrode of the 8th NMOS tube 3 output terminal of formation the 4th phase inverter.The input end of the 4th phase inverter is connected with the output terminal of the 3rd phase inverter, and output terminal is connected with the output terminal of calibration circuit to be measured.
The grid of NMOS standard feedback gain tube 6 is connected with the output of the 7th feedback control component, and drain electrode is connected with the output terminal of the 3rd phase inverter, and the unstable degradation effect of positive bias temperature does not occur NMOS standard feedback gain tube 6.
The grid of the 8th NMOS feedback transistor 5 is connected with the output terminal of calibration circuit to be measured, source ground, and drain electrode is connected with the source electrode of NMOS standard feedback gain tube 6, for reacting the feedback gain of NMOS standard feedback gain tube 6, and outputting standard hysteresis voltage signal.
The grid of PMOS standard feedback gain tube 7 is connected with the output of the 7th feedback control component, and drain electrode is connected with the output terminal of the 3rd phase inverter, and the unstable degradation effect of negative temperature bias does not occur PMOS standard feedback gain tube 7.。
The grid of the 7th PMOS feedback transistor 8 is connected with the output terminal of calibration circuit to be measured, and source electrode connects power supply, and drain electrode is connected with the source electrode of PMOS standard feedback gain tube 7, for reacting the feedback gain of PMOS standard feedback gain tube 7, and outputting standard hysteresis voltage signal.
The control method of (2.2) second feedback control component and line construction
The input of the second feedback control component comprises the 0th control signal, the first control signal, the first feedback gain adjustment voltage, the second feedback gain adjustment voltage, and its output comprises the 3rd output terminal and the 4th output terminal.3rd output terminal is connected with the grid of NMOS standard feedback gain tube 6, and the 4th output terminal is connected with the grid of PMOS standard feedback gain tube 7.
When the first control signal and the 0th control signal are all low level, the grid of PMOS standard feedback gain tube 7 connects power supply,, there is not Bias Temperature instability degradation effect for making NMOS standard feedback gain tube 6 or PMOS standard feedback gain tube 7 in the grounded-grid of NMOS standard feedback gain tube 6.
When the first control signal is low level, when 0th control signal is high level, the grid of PMOS standard feedback gain tube 7 connects the second feedback gain adjustment voltage, and the grid of NMOS standard feedback gain tube 6 connects the first feedback gain adjustment voltage, for outputting standard hysteresis voltage signal.
When the first control signal is high level, when the 0th control signal is low level, the grid of PMOS standard feedback gain tube 7 disconnects, and the grid of NMOS standard feedback gain tube 6 disconnects, for terminating or tentative test.
When the first control signal and the 0th control signal are all high level, the grid of PMOS standard feedback gain tube 7 connects power supply,, there is not Bias Temperature instability degradation effect for making NMOS standard feedback gain tube 6 or PMOS standard feedback gain tube 7 in the grounded-grid of NMOS standard feedback gain tube 6.
Second feedback control component comprises the 9th PMOS 9, the 9th NMOS tube 10, the tenth NMOS tube 11, the tenth PMOS the 12, the 11 PMOS the 13, the 11 NMOS tube the 14, the 12 NMOS tube the 15, the 12 PMOS 16 and not gate.
9th PMOS 9 is connected with the grid of the 9th NMOS tube 10, for receiving the first control signal.The source ground of the 9th NMOS tube 10, the source electrode of the 9th PMOS 9 is for receiving the first feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of the 9th NMOS tube 10.The grid of the tenth PMOS 12 is connected by the grid of not gate with the tenth NMOS tube 11, for receiving the 0th control signal.The source ground of the tenth PMOS 12, the source electrode of the tenth NMOS tube 11 is connected with the drain electrode of the 9th NMOS tube 10, and formation first output terminal that to be connected with the drain electrode of the tenth PMOS 12 of draining is connected with the grid of NMOS feedback gain control tube 6.
The grid of the 11 NMOS tube 14 is connected by the grid of not gate with the 11 PMOS 13, for receiving the first control signal.The source electrode of the 11 NMOS tube 14 connects power supply, and the source electrode of the 11 PMOS 13 is for receiving the second feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of the 11 NMOS tube 14.12 NMOS tube 15 is connected with the grid of the 12 PMOS 16, for receiving the 0th control signal.The source electrode of the 12 PMOS 16 connects power supply, and the source electrode of the 12 NMOS tube 15 is connected with the drain electrode of the 11 NMOS tube 14, and formation second output terminal that to be connected with the drain electrode of the 12 PMOS 16 of draining is connected with the grid of PMOS feedback gain control tube 7.
It is more than the detailed description about proving installation internal wiring structure of the present invention, technical scheme of the present invention is using the NMOS feedback gain control tube in this schmitt trigger or PMOS feedback gain control tube as backfeed loop components and parts to be measured, stress transmission of being degenerated by BTI becomes the feedback gain of this schmitt trigger to degenerate, thus converts the change of this schmitt trigger hysteresis voltage to.Step and the specific implementation process of following method of testing of the present invention are described further.
The invention allows for the method for testing that a kind of MOS device Bias Temperature instability is degenerated, comprise the steps:
Step one: for circuit under test, the backfeed loop components and parts utilizing the first feedback control component inner to be measured to first this schmitt trigger apply stress; Simultaneously for reference calibrations circuit, the second feedback control component is utilized not apply stress to the backfeed loop components and parts of second this schmitt trigger inside;
Step 2: the backfeed loop components and parts in first this schmitt trigger Bias Temperature instability will occur under effect of stress and degenerate, thus change first this schmitt trigger feedback gain, and then changing the hysteresis voltage of first this schmitt trigger, circuit under test exports the actual hysteresis voltage signal after degenerating; There is not Bias Temperature instability and degenerate in the backfeed loop components and parts of second this schmitt trigger inside, reference calibrations circuit outputting standard hysteresis voltage signal;
Step 3: utilize testing circuit to contrast actual hysteresis voltage signal and standard hysteresis voltage signal, calculate the pulse width that there are differences between actual hysteresis voltage signal and standard hysteresis voltage signal;
Step 4: pulse width is scaled Bias Temperature instability degree of degeneration.
In conjunction with the line construction of the invention described above proving installation, be divided into four kinds to the pattern of first this schmitt trigger applying Bias Temperature instability degeneration stress in the present embodiment, NBTI applies stress mode, PBTI applies stress mode, test pattern and prohibited mode.The control signal feature list of each pattern is as shown in the following Table 1:
Table 1 control signal function
See above table 1, be in PBTI stress mode ({ CS1, CS0}=00) in: the 5th PMOS 33, the 6th PMOS 36 are opened, 5th NMOS tube 34 and the 6th NMOS tube 35 are closed, now node A (i.e. the grid of PMOS feedback gain control tube 27) voltage is that VDD, PMOS feedback gain control tube 27 is not in the stress applying stage; 3rd NMOS tube 30, the 4th NMOS tube 31 are closed simultaneously, 3rd PMOS 29 and the 4th PMOS 32 are opened, now Node B (grid of NMOS feedback gain control tube 26) voltage is that VDD, NMOS feedback gain control tube 26 pipe is in applying stage of stress.
Test pattern ({ CS1, CS0}=01): the 5th PMOS 33, the 6th NMOS tube 35 are opened, 5th NMOS tube 34 and the 6th PMOS 36 are closed, now node A voltage is the second outside feedback gain adjustment voltage Vbiasp, and PMOS feedback gain control tube 27 will be in test pattern; 3rd PMOS 29, the 4th NMOS tube 31 are opened simultaneously, and the 3rd NMOS tube 30 and the 4th PMOS 32 are closed, and now node B voltage is the first feedback gain adjustment voltage Vbiasn, and NMOS feedback gain control tube 26 pipe is in test pattern.That is, NBTI and PBTI test belongs to a pattern together.
Prohibited mode (CS1, CS0}=10): forbid occurring this kind of control signal in the whole course of work.
NBTI stress mode ({ CS1, CS0}=11): the 5th NMOS tube 34, the 6th NMOS tube 35 are opened, 5th PMOS 33 and the 6th PMOS 36 are closed, and now node A voltage is that GND, PMOS feedback gain control tube 27 is in the NBTI stress applying stage; 3rd PMOS 29, the 4th PMOS 32 are closed simultaneously, and the 3rd NMOS tube 30 and the 4th NMOS tube 31 are opened, and now node B voltage is GND, do not apply stress to NMOS feedback gain control tube 26 pipe.
The accurate circuit of reference member comprises second this schmitt trigger and the second feedback control component, and the line construction of second this schmitt trigger is identical with the line construction of first this schmitt trigger.While first this schmitt trigger is applied in stress, second this schmitt trigger is not applied in stress, and its standard hysteresis voltage signal exported is used for the foundation as the actual hysteresis voltage signal of comparison.Correspondingly, reference calibrations circuit has three kinds of mode of operations: test pattern, not by stress mode and prohibited mode.Its control signal feature list is as shown in the following Table 2:
Table 2 reference circuit control signal feature list
See Fig. 2, not by under stress mode, { CS1, CS0}=00: the ten one PMOS the 13, the 12 PMOS 16 is opened, 11 NMOS tube the 14 and the 12 NMOS tube 15 is closed, now node C (i.e. the grid of PMOS standard feedback gain tube 7) voltage is that VDD, PMOS standard feedback gain tube 7 is not in the stress applying stage; 9th NMOS tube 10, the tenth NMOS tube 11 are closed simultaneously, 9th PMOS 9 and the tenth PMOS 12 are opened, now node D (i.e. the grid of NMOS standard feedback gain tube 6) voltage is that GND, NMOS standard feedback gain tube 6 pipe is in and does not apply stress state.
Under test pattern, CS1, CS0}=01: the 11 PMOS the 13, the 12 NMOS tube 15 is opened, the 11 NMOS tube the 14 and the 12 PMOS 16 is closed, now node C voltage is that outside regulation voltage Vbiasp, PMOS standard feedback gain tube 7 will be in test pattern; 9th PMOS 9, the tenth NMOS tube 11 are opened simultaneously, and the 9th NMOS tube 10 and the tenth PMOS 12 are closed, and now node D voltage is that Vbiasn, NMOS standard feedback gain tube 6 pipe is in test pattern.That is, NBTI and PBTI test belongs to a pattern together.
Under prohibited mode, { CS1, CS0}=10: forbid occurring this kind of control signal in the whole course of work.
Not by under stress mode, CS1, CS0}=11: the 11 NMOS tube the 14, the 12 NMOS tube 15 is opened, the 11 PMOS the 13 and the 12 PMOS 16 is closed, now node C voltage is that VDD, PMOS standard feedback gain tube 7 is in the non-NBTI stress applying stage; Simultaneously the 9th PMOS 9, the tenth PMOS 12 are closed, and the 9th NMOS tube 10 and the tenth NMOS tube 11 are opened, and now node D voltage is that GND, NMOS standard feedback gain tube 6 pipe is in and does not apply stage of stress.As can be seen here, no matter why CS1CS0 is worth, and NMOS standard feedback gain tube 6 and PMOS standard feedback gain tube 7 all there will not be by stress state, therefore can be used as the reference of circuit to be tested.
Whole test process comprises and first carries out stress applying, and then tests.The waveform of its test process as shown in Figure 4 and Figure 5,
NBTI degradation testing process:
Will CS1, CS0} are arranged to 11, apply stress to PMOS standard feedback gain tube 7 pipe, and CS1, CS0}=00, stopping applying stress, like this repeatedly until terminate according to stress applying condition.
At the end of stress applying process, by { CS1, CS0} are arranged to 01, and Vin starts to drop to GND gradually from VDD, and fall off rate is controlled by outside source simultaneously.Vout1 is that the reference calibrations circuit not applying stress exports, and Vout2 exports for applying overstress testing circuit.Because NBTI degeneration can cause Vout2 to have a delay relative to Vout1, therefore Vout1 and Vout2 can produce a high level pulse after XOR gate, pulsewidths representative device performance degeneration degree.
PBTI degradation testing process:
Will CS1, CS0} are arranged to 00, and to NMOS standard feedback gain tube 6 pipe applying stress, { CS1, CS0}=11, stopping applying stress.According to stress applying condition so repeatedly until stress applies to terminate.
At the end of stress applies, by { CS1, CS0} are arranged to 01, and Vin starts to rise to VDD gradually from GND, and the rise time is by external control simultaneously.Vout1 is that the reference calibrations circuit not applying stress exports, and Vout2 exports for applying overstress testing circuit.Because PBTI degeneration can cause Vout2 to have a delay relative to Vout1.Vout1 and Vout2 convert delay-time difference to a high level pulse through XOR gate, pulsewidths representative device performance degeneration degree.
More than set forth the concrete control mode of method of testing that MOS device Bias Temperature instability of the present invention is degenerated, below in conjunction with for NBTI degradation testing process, specific explanations illustrates process and the principle of method of testing.PBTI degradation testing process and principle thereof and NBTI degradation testing process similar.
For NBTI degradation testing process, after PMOS feedback gain control tube 27 is applied in stress, the threshold voltage of PMOS feedback gain control tube 27 can increase along with stress time, because PMOS feedback gain control tube 27 is positioned at (arrow see Fig. 2) on the backfeed loop of this schmitt trigger of test circuit, therefore the NBTI institute that degenerates causes the change of PMOS feedback gain control tube 27 threshold voltage can cause first this schmitt trigger feedback gain change, thus causes the hysteresis voltage of first this schmitt trigger to change.
When circuit under test and reference calibrations circuit input identical Vin signal (triangular wave) simultaneously, because the hysteresis voltage of first this schmitt trigger in circuit under test changes, the actual hysteresis voltage signal of output is caused to shift to an earlier date relative to the rising edge of the standard hysteresis voltage signal of the output of reference calibrations circuit.Finally utilize XOR gate to compare two output waveforms, can obtain output pulse, this pulse width is the Timing Advance of circuit under test relative to reference calibrations circuit rising edge, so this pulse width can react the degree of degeneration of PMOS feedback gain control tube 27.
When PMOS feedback gain control tube 27 occurs to degenerate (threshold voltage changes), the grid effective voltage being equivalent to PMOS feedback gain control tube 27 changes.See Fig. 6, for same input Vin, the curve of output (i.e. actual hysteresis voltage signal) of first this schmitt trigger can offset.
Suppose that Vbiasp is a fixed value, ignore the voltage drop (transmission gate that available complementary cmos pipe is formed substitutes single metal-oxide-semiconductor transmission gate) that the 5th PMOS 33 and the 6th NMOS tube 35 cause, PMOS feedback gain control tube 27 grid not adding the voltage occurred when degenerating is Vbiasp, the overdrive voltage of PMOS feedback gain control tube 27 is Vbiasp-Vth0, wherein Vth0 is the threshold voltage that PMOS feedback gain control tube 27 does not occur when degenerating, and is a constant.Suppose that the degeneration of △ Vth occurs PMOS feedback gain control tube 27, then effective overdrive voltage of PMOS feedback gain control tube 27 is Vbiasp-Vth0-△ Vth.Different overdrive voltages can cause the change of hysteresis voltage in as above figure, the hysteresis voltage longitudinal axis voltage that the reaction intersection point that is input Vin and output is corresponding in figure 6 surely.Can know that PMOS feedback gain control tube 27 is degenerated the relation curve of (threshold voltage change) and pulse width by circuit simulation.When reality is tested, the relation curve reverse push obtained by emulation after obtaining pulse width derives the degradation values of threshold voltage.
Protection content of the present invention is not limited to above embodiment.Under the spirit and scope not deviating from inventive concept, the change that those skilled in the art can expect and advantage are all included in the present invention, and are protection domain with appending claims.
Claims (7)
1. a proving installation for MOS device Bias Temperature instability degeneration, is characterized in that, comprising: circuit under test, reference calibrations circuit and testing circuit; The output of described circuit under test and described reference calibrations circuit is connected to described testing circuit simultaneously;
The inside of described circuit under test arranges the first feedback control component and first this schmitt trigger, described first feedback control component is connected with described first this schmitt trigger, described first feedback control component applies stress to backfeed loop components and parts to be measured in described first this schmitt trigger thus makes described backfeed loop components and parts generation Bias Temperature instability degradation effect, realize the feedback gain changing described first this schmitt trigger, and then change the hysteresis voltage of described first this schmitt trigger, described circuit under test exports the actual hysteresis voltage signal after degenerating,
Described reference calibrations inside circuit arranges the second feedback control component and second this schmitt trigger, and described second feedback control component is connected with described second this schmitt trigger; While described first this schmitt trigger is applied in stress, described second feedback control component makes described second this schmitt trigger not be applied in stress, the feedback gain of described second this schmitt trigger remains unchanged thus the hysteresis voltage of described second this schmitt trigger is remained unchanged, described reference calibrations circuit outputting standard hysteresis voltage signal;
Described testing circuit by comparing and measuring the difference between described actual hysteresis voltage signal and described normative reference hysteresis voltage signal, for reflecting the Bias Temperature instability degree of degeneration of described backfeed loop components and parts.
2. the proving installation of MOS device Bias Temperature instability degeneration as claimed in claim 1, it is characterized in that, described testing circuit is XOR gate, the input of described XOR gate receives described actual hysteresis voltage signal and described standard hysteresis voltage signal respectively, when level between described actual hysteresis voltage signal and described standard hysteresis voltage signal there are differences, described XOR gate exports high level signal, by measuring the pulse width of described high level signal to test the Bias Temperature instability degree of degeneration of described backfeed loop components and parts.
3. the proving installation of MOS device Bias Temperature instability degeneration as claimed in claim 1, it is characterized in that, described first feedback control component comprises the 3rd PMOS (29), the 3rd NMOS tube (30), the 4th NMOS tube (31), the 4th PMOS (32), the 5th PMOS (33), the 5th NMOS tube (34), the 6th NMOS tube (35) and the 6th PMOS (36);
Described 3rd PMOS (29) is connected, for receiving the first control signal with the grid of described 3rd NMOS tube (30); The source ground of described 3rd NMOS tube (30), the source electrode of described 3rd PMOS (29) is for receiving the first feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 3rd NMOS tube (30); Described 4th NMOS tube (31) is connected with the grid of described 4th PMOS (32), for receiving the 0th control signal; The source electrode of described 4th PMOS (32) connects power supply, the source electrode of described 4th NMOS tube (31) is connected with the drain electrode of described 3rd NMOS tube (30), and drain electrode formation first output terminal that to be connected with the drain electrode of described 4th PMOS (32) is connected with described first this schmitt trigger;
Described 5th PMOS (33) is connected, for receiving the first control signal with the grid of described 5th NMOS tube (34); The source ground of described 5th NMOS tube (34), the source electrode of described 5th PMOS (33) is for receiving the second feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 5th NMOS tube (34); Described 6th NMOS tube (35) is connected with the grid of described 6th PMOS (36), for receiving the 0th control signal; The source electrode of described 6th PMOS (36) connects power supply, the source electrode of described 6th NMOS tube (35) is connected with the drain electrode of described 5th NMOS tube (34), and drain electrode formation second output terminal that to be connected with the drain electrode of described 6th PMOS (36) is connected with described first this schmitt trigger.
4. the proving installation of MOS device Bias Temperature instability degeneration as claimed in claim 1, it is characterized in that, described second feedback control component comprises the 9th PMOS (9), the 9th NMOS tube (10), the tenth NMOS tube (11), the tenth PMOS (12), the 11 PMOS (13), the 11 NMOS tube (14), the 12 NMOS tube (15), the 12 PMOS (16) and not gate;
Described 9th PMOS (9) is connected, for receiving the first control signal with the grid of described 9th NMOS tube (10); The source ground of described 9th NMOS tube (10), the source electrode of described 9th PMOS (9) is for receiving the first feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 9th NMOS tube (10); The grid of described tenth PMOS (12) is connected, for receiving the 0th control signal by the grid of not gate with described tenth NMOS tube (11); The source ground of described tenth PMOS (12), the source electrode of described tenth NMOS tube (11) is connected with the drain electrode of described 9th NMOS tube (10), and drain electrode formation first output terminal that to be connected with the drain electrode of described tenth PMOS (12) is connected with described second this schmitt trigger;
The grid of described 11 NMOS tube (14) is connected, for receiving the first control signal by the grid of not gate with described 11 PMOS (13); The source electrode of described 11 NMOS tube (14) connects power supply, and the source electrode of described 11 PMOS (13) is for receiving the second feedback gain adjustment voltage, and drain electrode is connected with the drain electrode of described 11 NMOS tube (14); Described 12 NMOS tube (15) is connected with the grid of described 12 PMOS (16), for receiving the 0th control signal; The source electrode of described 12 PMOS (16) connects power supply, the source electrode of described 12 NMOS tube (15) is connected with the drain electrode of described 11 NMOS tube (14), and drain electrode formation second output terminal that to be connected with the drain electrode of described 12 PMOS (16) is connected with described second this schmitt trigger.
5. a method of testing for MOS device Bias Temperature instability degeneration, is characterized in that, comprise the steps:
Step one: for circuit under test, the backfeed loop components and parts utilizing the first feedback control component inner to be measured to first this schmitt trigger apply stress; Simultaneously for reference calibrations circuit, the second feedback control component is utilized not apply stress to the backfeed loop components and parts of second this schmitt trigger inside;
Step 2: the backfeed loop components and parts in described first this schmitt trigger Bias Temperature instability will occur under effect of stress and degenerate, thus change described first this schmitt trigger feedback gain, and then changing the hysteresis voltage of described first this schmitt trigger, described circuit under test exports the actual hysteresis voltage signal after degenerating; There is not Bias Temperature instability and degenerate in the backfeed loop components and parts of described second this schmitt trigger inside, described reference calibrations circuit outputting standard hysteresis voltage signal;
Step 3: utilize testing circuit to contrast described actual hysteresis voltage signal and described standard hysteresis voltage signal, calculate the pulse width that there are differences between described actual hysteresis voltage signal and described standard hysteresis voltage signal;
Step 4: described pulse width is scaled Bias Temperature instability degree of degeneration.
6. the method for testing of MOS device Bias Temperature instability degeneration as claimed in claim 5, it is characterized in that, the described pulse width that there are differences be XOR gate export pulse width, described XOR gate be input as described actual hysteresis voltage signal and described standard hysteresis voltage signal.
7. the method for testing of MOS device Bias Temperature instability degeneration as claimed in claim 5, it is characterized in that, the conversion method described pulse width being scaled Bias Temperature instability degree of degeneration is: the knots modification of the described actual hysteresis voltage signal that converts according to described pulse width, and determines actual degradation values according to the curve carrying out emulating degeneration voltage and the hysteresis voltage obtained to circuit.
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