CN103576067A - Bias voltage temperature instability testing circuit and testing method thereof - Google Patents
Bias voltage temperature instability testing circuit and testing method thereof Download PDFInfo
- Publication number
- CN103576067A CN103576067A CN201210264937.0A CN201210264937A CN103576067A CN 103576067 A CN103576067 A CN 103576067A CN 201210264937 A CN201210264937 A CN 201210264937A CN 103576067 A CN103576067 A CN 103576067A
- Authority
- CN
- China
- Prior art keywords
- voltage
- voltage end
- temperature instability
- measured
- test circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a bias voltage temperature instability testing circuit which comprises a circular vibrator circuit. The vibrator circuit comprises n grades of testing circuits which are the same in structure. Each testing circuit comprises a first node, a second node and a third node. The third node of each testing circuit is connected with the first node of a former testing circuit. Each testing circuit comprises a PMOS tube to be tested, an NMOS tube to be tested, a switch PMOS tube, a switch NMOS tube and at least one pair of partial pressure PMOS tube and partial pressure NMOS tube, wherein the PMOS tube to be tested and the NMOS tube to be tested are complementary, the switch PMOS tube and the switch NMOS tube are complementary, and the partial pressure PMOS tube and the partial pressure NMOS tube are complementary. The invention further discloses a testing method for the bias voltage temperature instability testing circuit. The method comprises the steps of providing the bias voltage temperature instability testing circuit, testing the negative bias pressure temperature instability of the PMOS tube to be tested and testing the positive bias pressure temperature instability of the NMOS tube to be tested. The bias voltage temperature instability testing circuit can test the negative bias pressure temperature instability of the PMOS tube to be tested and the positive bias pressure temperature instability of the NMOS tube to be tested.
Description
Technical field
The present invention relates to IC reliability field tests, particularly relate to a kind of bias voltage temperature instability test circuit and method of testing thereof.
Background technology
Bias voltage temperature instability (Bias Temperature Instability is called for short BTI) is one of basic problem of complementary metal oxide semiconductor (CMOS) (Complementary Metal Oxide Semiconductor is called for short CMOS) reliability.Wherein, BTI is divided into Negative Bias Temperature Instability (Negative Bias Temperature Instability is called for short NBTI) and positive bias temperature instability (Positive Bias Temperature Instability is called for short PBTI).NBTI refers to the degeneration of a series of electrical parameters that at high temperature PMOS pipe applied to minus gate voltage and cause, the production process of NBTI effect relates generally to generation and the passivation of positive charge, be the generation of interface trapped charge and positive fixed oxide charges and the diffusion process of diffusate, hydrogen and steam are two kinds of main matter that cause NBTI.The CMOS of the nanoscale forming for the gate medium of silicon materials, the NBTI of PMOS pipe is the main cause that affects device lifetime.But the CMOS to high-k gate dielectric, the PBTI of the NBTI of PMOS pipe and NMOS pipe is the major reason that affects device lifetime.
Fig. 1 is the schematic diagram of bias voltage temperature instability test circuit of the prior art, this bias voltage temperature instability test circuit is based on ring oscillator circuit, by test PMOS pipe and NMOS pipe, the annular before and after the voltage of exerting pressure is reverberated the conversion of device circuit oscillation frequency, the Negative Bias Temperature Instability of test PMOS pipe and the positive bias temperature instability of NMOS pipe, but this bias voltage temperature instability test circuit cannot be distinguished the Negative Bias Temperature Instability of PMOS pipe and the degree of the positive bias temperature instability of NMOS pipe to circuit oscillation frequency influence.
Therefore, how to provide a kind of test circuit and the method for testing that can test the Negative Bias Temperature Instability of PMOS pipe and the positive bias temperature instability of NMOS pipe, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the invention is to, a kind of bias voltage temperature instability test circuit and the method for testing thereof that can test the Negative Bias Temperature Instability of PMOS pipe and the positive bias temperature instability of NMOS pipe is provided.
For solving the problems of the technologies described above, the invention provides a kind of bias voltage temperature instability test circuit, comprising:
Annular is reverberated device circuit, described ring oscillator circuit comprises n level test circuit, the structure of every grade of test circuit is identical, each test circuit comprises first node, Section Point and the 3rd node, the first node of each test circuit is connected with the 3rd node of its last test circuit, and n is positive integer; Wherein
Each test circuit comprises complementary PMOS pipe to be measured and NMOS to be measured pipe, complementary switch P metal-oxide-semiconductor and switch NMOS pipe and at least one pair of complementary dividing potential drop PMOS pipe and dividing potential drop NMOS pipe, and the source electrode of described PMOS pipe to be measured connects the first voltage end, grid connects first node, the source electrode of described NMOS pipe to be measured connects low level, grid connects first node, the source electrode of described switch P metal-oxide-semiconductor connects the first voltage end, grid connects second voltage end, drain electrode connects the 3rd node, the source electrode of described switch NMOS pipe connects low level end, grid connects tertiary voltage end, grounded drain the 3rd node, the drain electrode of described dividing potential drop PMOS pipe connects Section Point, grid connects the 4th voltage end, source electrode connects the drain electrode of described PMOS pipe to be measured, the drain electrode of described dividing potential drop NMOS pipe connects Section Point, grid connects the 5th voltage end, source electrode connects the drain electrode of described NMOS pipe to be measured.
Further, between the 3rd node of described each test circuit and the first node of its next test circuit, access a transmission gate.
What further, described transmission gate was a pair of complementation puts big pmos and amplifies NMOS pipe.
Further, described in, put the grid of big pmos and the grid of described amplification NMOS pipe connects the 6th voltage end.
Further, n >=3.
Further, the present invention also provides a kind of method of testing of bias voltage temperature instability test circuit, comprising:
Above-mentioned bias voltage temperature instability test circuit is provided;
Test the Negative Bias Temperature Instability of PMOS pipe to be measured;
Test the positive bias temperature instability of NMOS pipe to be measured.
Further, the Negative Bias Temperature Instability of described test PMOS pipe to be measured comprises:
PMOS pipe to be measured is in pressure state, and described the first voltage end, second voltage end and the 4th voltage end are stress voltage, and tertiary voltage end is operating voltage, the 5th voltage end ground connection, and first node connects low level;
PMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end and the 5th voltage end are operating voltage, tertiary voltage end ground connection, described the 4th voltage end ground connection.
Further, the positive bias temperature instability of described test NMOS pipe to be measured comprises:
NMOS pipe to be measured is in pressure state, and described the first voltage end and the 4th voltage end are stress voltage, second voltage end, tertiary voltage end and the 5th voltage end ground connection, and first node connects stress voltage;
NMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end and the 5th voltage end are operating voltage, tertiary voltage end and the 4th voltage end ground connection.
Further, described stress voltage is greater than described operating voltage.
Further, the variation that described bias voltage temperature instability is reverberated device circuit oscillation frequency by annular characterizes, or by annular, reverberates the curent change of PMOS to be measured pipe and NMOS pipe to be measured in device circuit and characterize.
Further, the present invention also provides a kind of method of testing of bias voltage temperature instability test circuit, comprising:
Above-mentioned bias voltage temperature instability test circuit is provided;
Between the 3rd node of described each test circuit and the first node of its next test circuit, access a transmission gate, described transmission gate is putting big pmos and amplifying NMOS pipe of a pair of complementation, described in put the grid of big pmos and the grid of described amplification NMOS pipe connects the 6th voltage end;
Test the Negative Bias Temperature Instability of PMOS pipe to be measured;
Test the positive bias temperature instability of NMOS pipe to be measured.
Further, the Negative Bias Temperature Instability of described test PMOS pipe to be measured comprises:
PMOS pipe to be measured is in pressure state, and described the first voltage end and the 4th voltage end second voltage end are stress voltage, and tertiary voltage end and the 6th voltage end are operating voltage, the 5th voltage end ground connection, and first node connects low level;
PMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end and the 5th voltage end are operating voltage, tertiary voltage end, the 4th voltage end and the 6th voltage end ground connection.
Further, the positive bias temperature instability of described test NMOS pipe to be measured comprises:
NMOS pipe to be measured is in pressure state, and described the first voltage end and the 4th voltage end are stress voltage, second voltage end, tertiary voltage end and the 5th voltage end ground connection, and the 6th voltage end is operating voltage, first node connects stress voltage;
NMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end, the 5th voltage end and the 6th voltage end are operating voltage, tertiary voltage end and the 4th voltage end ground connection.
Further, described stress voltage is greater than described operating voltage.
Further, the variation that described bias voltage temperature instability is reverberated device circuit oscillation frequency by annular characterizes, or by annular, reverberates the curent change of PMOS to be measured pipe and NMOS pipe to be measured in device circuit and characterize.
Compared with prior art, bias voltage temperature instability test circuit provided by the invention and method of testing thereof have the following advantages:
1, bias voltage temperature instability test circuit provided by the invention and method of testing thereof, this bias voltage temperature instability test circuit adds with PMOS pipe to be measured and NMOS to be measured manages switch P metal-oxide-semiconductor in parallel and switch NMOS pipe, compared with prior art, the present invention is by under difference controlled pressure state and test mode, the state that opens or closes of switch P metal-oxide-semiconductor and switch NMOS pipe, and the source electrode of PMOS pipe to be measured and NMOS pipe to be measured, grid, the voltage that drain electrode access is different, thereby can measure the Negative Bias Temperature Instability of PMOS pipe to be measured and the positive bias temperature instability of NMOS pipe to be measured.
2, bias voltage temperature instability test circuit provided by the invention and method of testing thereof, the series connection between PMOS pipe to be measured and NMOS pipe to be measured of this bias voltage temperature instability test circuit adds dividing potential drop PMOS pipe and dividing potential drop NMOS pipe, compared with prior art, this dividing potential drop PMOS pipe and dividing potential drop NMOS pipe can be shared the voltage in circuit, improve the reliability of circuit.
3, bias voltage temperature instability test circuit provided by the invention and method of testing thereof, this bias voltage temperature instability test circuit adds transmission gate, and compared with prior art, this transmission gate can amplifying signal, increases the susceptibility of bias voltage temperature instability test.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of bias voltage temperature instability test circuit of the prior art;
Fig. 2 is the schematic diagram of bias voltage temperature instability test circuit in one embodiment of the invention;
Fig. 3 is the process flow diagram of bias voltage temperature instability test circuit method of testing in one embodiment of the invention;
Fig. 4 a-Fig. 4 d is the schematic diagram of bias voltage temperature instability test circuit method of testing in one embodiment of the invention;
Fig. 5 is the schematic diagram of bias voltage temperature instability test circuit in another embodiment of the present invention;
Fig. 6 a-Fig. 6 d is the schematic diagram of bias voltage temperature instability test circuit method of testing in another embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, bias voltage temperature instability test circuit of the present invention and method of testing thereof are described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to the restriction of relevant system or relevant business, by an embodiment, change into another embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with reference to accompanying drawing, with way of example, the present invention is more specifically described.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of bias voltage temperature instability test circuit and method of testing thereof are provided, this bias voltage temperature instability test circuit comprises that annular reverberates device circuit, described ring oscillator circuit comprises n level test circuit, each test circuit comprises PMOS pipe to be measured and the NMOS to be measured pipe of a pair of complementation, the switch P metal-oxide-semiconductor of a pair of complementation and switch NMOS pipe, by the state that opens or closes of gauge tap PMOS pipe and switch NMOS pipe, make PMOS pipe to be measured and NMOS pipe to be measured in pressure state or test mode.
In conjunction with above-mentioned core concept, the invention provides a kind of bias voltage temperature instability test circuit, comprising:
Annular is reverberated device circuit, described ring oscillator circuit comprises n level test circuit, the structure of every grade of test circuit is identical, each test circuit comprises first node, Section Point and the 3rd node, the 3rd node of each test circuit is connected with the first node of its last test circuit, and n is positive integer; Wherein
Each test circuit comprises complementary PMOS pipe to be measured and NMOS to be measured pipe, complementary switch P metal-oxide-semiconductor and switch NMOS pipe and at least one pair of complementary dividing potential drop PMOS pipe and dividing potential drop NMOS pipe, and the source electrode of described PMOS pipe to be measured connects the first voltage end, grid connects first node, the source electrode of described NMOS pipe to be measured connects low level, grid connects first node, the source electrode of described switch P metal-oxide-semiconductor connects the first voltage end, grid connects second voltage end, drain electrode connects the 3rd node, the source electrode of described switch NMOS pipe connects low level end, grid connects tertiary voltage end, grounded drain the 3rd node, the drain electrode of described dividing potential drop PMOS pipe connects Section Point, grid connects the 4th voltage end, source electrode connects the drain electrode of described PMOS pipe to be measured, the drain electrode of described dividing potential drop NMOS pipe connects Section Point, grid connects the 5th voltage end, source electrode connects the drain electrode of described NMOS pipe to be measured.
Further, in conjunction with above-mentioned bias voltage temperature instability test circuit, the present invention also provides a kind of method of testing, comprises the following steps:
Step S01, provides above-mentioned bias voltage temperature instability test circuit;
Step S02, the Negative Bias Temperature Instability of testing PMOS pipe to be measured;
Step S03, the positive bias temperature instability of testing NMOS pipe to be measured.
Below enumerate several embodiment of described a kind of bias voltage temperature instability test circuit and method of testing thereof, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by those of ordinary skills' routine techniques means are also within thought range of the present invention.
[the first embodiment]
Below please refer to Fig. 2, it is the schematic diagram of the bias voltage temperature instability test circuit of invention the first embodiment.
Bias voltage temperature instability test circuit of the present invention comprises that annular reverberates device circuit, n level test circuit, and every grade of test circuit comprises that the PMOS pipe to be measured of a pair of complementation and NMOS to be measured pipe, the switch P metal-oxide-semiconductor of a pair of complementation and dividing potential drop PMOS pipe and the dividing potential drop NMOS of switch NMOS pipe and a pair of complementation manage.
As shown in Figure 2, in the present embodiment, described bias voltage temperature instability test circuit take annular reverberate device circuit as basis, described ring oscillator circuit comprises n level test circuit, and the structure of every grade of test circuit is identical, and wherein n is positive integer, in Fig. 2, S1 is the 1st grade of test circuit, and S2 is the 2nd grade of test circuit, and S3 is 3rd level test circuit.This ring oscillator circuit preferably also comprises necessary device, as phase inverter, in Fig. 2, does not specifically illustrate.Preferably, n >=3, if n is 5,10,15,20 etc.
The 2nd grade of test circuit of take is example, illustrates the structure of every grade of test circuit.As shown in Figure 2, the 2nd grade of test circuit comprises PMOS pipe PA2 to be measured and the NMOS to be measured pipe NA2 of a pair of complementation, the dividing potential drop PMOS pipe PB2 of a pair of complementation and dividing potential drop NMOS pipe NB2, switch P metal-oxide-semiconductor PC2 and switch NMOS pipe NC2 with a pair of complementation, also comprise first node a2, Section Point b2 and the 3rd node c2, the first node a2 of the 2nd grade of test circuit is connected with the 3rd node c1 of the 1st grade of test circuit.Dividing potential drop PMOS pipe PB2 and dividing potential drop NMOS pipe NB2 can share the voltage in circuit, and the voltage difference between Section Point b2 and the 3rd node c2 is reduced, and improve the reliability of circuit.Can also between PMOS pipe PA2 to be measured and NMOS to be measured pipe NA2, access a plurality of dividing potential drop PMOS pipes and a plurality of dividing potential drop NMOS pipe, with further dividing potential drop.
The PMOS pipe source electrode of PA2 to be measured and the source electrode of switch P metal-oxide-semiconductor PC2 meet the first voltage end V1, the source electrode of the source electrode of NMOS pipe NA2 to be measured and switch NMOS pipe NC2 connects low level, the grid of the grid of PMOS pipe PA2 to be measured and NMOS to be measured pipe NA2 links together by first node a2, and is connected with the 3rd node c1 of the 1st grade.The grid of switch P metal-oxide-semiconductor PC2 is connected with second voltage end V2, and the grid of switch NMOS pipe NC2 is connected with tertiary voltage end V3, and the drain electrode of switch P metal-oxide-semiconductor PC2 is connected by the 3rd node c2 with the drain electrode of switch NMOS pipe NC2.The drain electrode that PMOS pipe PA2 is surveyed in the source electrode reception of dividing potential drop PMOS pipe PB2, the drain electrode that NMOS pipe NA2 is surveyed in the source electrode reception of dividing potential drop NMOS pipe NB2, the drain electrode of dividing potential drop PMOS pipe PB2 is connected by Section Point b2 with the drain electrode of dividing potential drop NMOS pipe NB2, the grid of dividing potential drop PMOS pipe PB2 meets the 4th voltage end V4, and the grid of dividing potential drop NMOS pipe NB2 meets the 5th voltage end V5.In the 1st grade of test circuit, the grid of the grid of PMOS pipe PA1 to be measured and NMOS to be measured pipe NA1 links together by first node a1, and is connected with the 3rd node cn of n level test circuit, makes this n level test circuit form annular and connects.
Below in conjunction with Fig. 3 and Fig. 4 a-Fig. 4 d, illustrate the method for testing of bias voltage temperature instability test circuit in the present embodiment.Fig. 3 is the process flow diagram of bias voltage temperature instability test circuit method of testing in one embodiment of the invention, and Fig. 4 a-Fig. 4 d is the schematic diagram of bias voltage temperature instability test circuit method of testing in one embodiment of the invention.
Step S11, provides the test circuit of the bias voltage temperature instability described in the present embodiment.
Step S12, the Negative Bias Temperature Instability of testing PMOS pipe to be measured.The Negative Bias Temperature Instability of described test PMOS pipe to be measured comprises:
PMOS pipe PA2 to be measured is in pressure state, as shown in Fig. 4 a, the first voltage end V1 and second voltage end V2 are stress voltage Vdd_stress, tertiary voltage end V3 is operating voltage Vdd, it is stress voltage Vdd_stress that first node a2 meets low level 0, the four voltage end V4, the 5th voltage end V5 ground connection GND, now, in the 2nd grade of test circuit, only have the pressure state of PMOS pipe PA2 to be measured in Negative Bias Temperature Instability;
PMOS pipe PA2 to be measured is in test mode, as shown in Figure 4 b, the first voltage end V1 and second voltage end V2 are operating voltage Vdd, tertiary voltage end V3 ground connection GND, the 4th voltage end V4 ground connection GND, the 5th voltage end V5 is operating voltage Vdd, now, in the 2nd grade of test circuit, dividing potential drop PMOS pipe PC2 and dividing potential drop NMOS pipe NC2 are in conventional open mode, and switch P metal-oxide-semiconductor PC2 and switch NMOS pipe NC2 are in conventional closed condition.Therefore, the instability of the 2nd grade of test circuit is that the Negative Bias Temperature Instability of PMOS to be measured pipe PA2 causes.So reverberate in device circuit in whole annular, the variation that the Negative Bias Temperature Instability of PMOS pipe to be measured can be reverberated device circuit oscillation frequency by annular characterizes, or characterizes by the curent change that annular is reverberated PMOS pipe to be measured in device circuit.
Step S13, the positive bias temperature instability of testing NMOS pipe to be measured.The positive bias temperature instability of described test NMOS pipe to be measured comprises:
NMOS pipe NA2 to be measured is in pressure state, as shown in Fig. 4 c, the first voltage end V1 is stress voltage Vdd_stress, second voltage end V2 and tertiary voltage end V3 ground connection GND, first node a2 meets stress voltage Vdd_stress, and the 4th voltage end V4 is stress voltage Vdd_stress, the 5th voltage end V5 ground connection GND, now, in the 2nd grade of test circuit, only have the pressure state of NMOS pipe NA2 to be measured in Negative Bias Temperature Instability;
NMOS pipe NA2 to be measured is in test mode, as shown in Fig. 4 d, the first voltage end V1 and second voltage end V2 are operating voltage Vdd, tertiary voltage end V3 ground connection GND, the 4th voltage end V4 ground connection GND, the 5th voltage end V5 is operating voltage Vdd, now, in the 2nd grade of test circuit, dividing potential drop PMOS pipe PC2 and dividing potential drop NMOS pipe NC2 are in conventional open mode, and switch P metal-oxide-semiconductor PC2 and switch NMOS pipe NC2 are in conventional closed condition.Therefore, the instability of the 2nd grade of test circuit is that the positive bias temperature instability of NMOS to be measured pipe NA2 causes.So reverberate in device circuit in whole annular, the variation that the positive bias temperature instability of NMOS pipe to be measured can be reverberated device circuit oscillation frequency by annular characterizes, or characterizes by the curent change that annular is reverberated NMOS pipe to be measured in device circuit.
In the present embodiment, stress voltage Vdd_stress is greater than operating voltage Vdd.The variation that bias voltage temperature instability can be reverberated device circuit oscillation frequency by annular characterizes, or by annular, reverberates the curent change of PMOS pipe to be measured and NMOS pipe to be measured in device circuit and characterize.
[the second embodiment]
Below please refer to Fig. 5, it is the schematic diagram of the bias voltage temperature instability test circuit of invention the second embodiment.The second embodiment is on the basis of the first embodiment, and difference is, the bias voltage temperature instability test circuit of the second embodiment also comprises transmission gate.Between the 3rd node of described each test circuit and the first node of its next test circuit, access a transmission gate.When k is 2, as shown in Figure 5, the 2nd grade of test circuit also comprises a transmission gate, and one end of transmission gate is connected with the 3rd node c2 in the 2nd grade of test circuit, and the other end of transmission gate is connected with the first node a3 in 3rd level test circuit.Transmission gate one end in n level test circuit is connected with the 3rd node cn in n level test circuit, and the other end is connected with the first node a1 in the 1st grade of test circuit, makes this n level test circuit form annular and connects.
Preferably, what transmission gate was a pair of complementation puts big pmos PD2 and amplifies NMOS pipe ND2, and the grid of putting big pmos PD2 meets the 6th voltage end V6 with the grid that amplifies NMOS pipe ND2.
Below in conjunction with Fig. 6 a-Fig. 6 d, illustrate the method for testing of bias voltage temperature instability test circuit in the present embodiment, Fig. 6 a-Fig. 6 d is the schematic diagram of bias voltage temperature instability test circuit method of testing in another embodiment of the present invention.The method of testing of the second embodiment is on the basis of the method for testing of the first embodiment, and difference is:
In step S12, the Negative Bias Temperature Instability of testing PMOS pipe to be measured also comprises: PMOS pipe PA2 to be measured is in test mode, and as shown in Figure 6 a, the 6th voltage end V6 is operating voltage Vdd; As shown in Figure 6 b, PMOS pipe to be measured is in test mode, and the 6th voltage end V6 is ground connection GND, now, amplifies NMOS pipe ND2 also in conventional closed condition, and the 6th voltage end V6 is ground connection GND, and the Negative Bias Temperature Instability of PMOS pipe to be measured is exaggerated.
In step S13, the positive bias temperature instability of testing NMOS pipe to be measured also comprises: NMOS pipe to be measured is in pressure state, and as shown in Fig. 6 c, the 6th voltage end V6 is operating voltage Vdd; NMOS pipe to be measured is in test mode, and as shown in Fig. 6 d, the 6th voltage end V6 is operating voltage Vdd, now, put big pmos PD2 also in conventional closed condition, the 6th voltage end V6 is operating voltage Vdd, and the positive bias temperature instability of NMOS pipe to be measured is exaggerated.
Bias voltage temperature instability test circuit in this second embodiment, can realize equally the function of bias voltage temperature instability test circuit in the first embodiment, can test the bias voltage temperature instability of the Negative Bias Temperature Instability of PMOS pipe and the positive bias temperature instability of NMOS pipe, but in the second embodiment by adding transmission gate, can reach and amplify instable signal, increase the beneficial effect of the susceptibility of bias voltage temperature instability test.
In sum, the invention provides a kind of bias voltage temperature instability test circuit and method of testing thereof, this bias voltage temperature instability test circuit comprises that annular reverberates device circuit, described ring oscillator circuit comprises n level test circuit, k level test circuit comprises PMOS pipe to be measured and the NMOS to be measured pipe of a pair of complementation, the switch P metal-oxide-semiconductor of a pair of complementation and switch NMOS pipe, by the state that opens or closes of gauge tap PMOS pipe and switch NMOS pipe, make PMOS pipe to be measured and NMOS pipe to be measured in pressure state or test mode.Compared with prior art, the bias voltage temperature instability test circuit that contains provided by the invention has the following advantages:
1, bias voltage temperature instability test circuit provided by the invention and method of testing thereof, this bias voltage temperature instability test circuit adds with PMOS pipe to be measured and NMOS to be measured manages switch P metal-oxide-semiconductor in parallel and switch NMOS pipe, compared with prior art, the present invention is by under difference controlled pressure state and test mode, the state that opens or closes of switch P metal-oxide-semiconductor and switch NMOS pipe, and the source electrode of PMOS pipe to be measured and NMOS pipe to be measured, grid, the voltage that drain electrode access is different, thereby can measure the Negative Bias Temperature Instability of PMOS pipe to be measured and the positive bias temperature instability of NMOS pipe to be measured.
2, bias voltage temperature instability test circuit provided by the invention and method of testing thereof, the series connection between PMOS pipe to be measured and NMOS pipe to be measured of this bias voltage temperature instability test circuit adds dividing potential drop PMOS pipe and dividing potential drop NMOS pipe, compared with prior art, this dividing potential drop PMOS pipe and dividing potential drop NMOS pipe can be shared the voltage in circuit, improve the reliability of circuit.
3, bias voltage temperature instability test circuit provided by the invention and method of testing thereof, this bias voltage temperature instability test circuit adds transmission gate, and compared with prior art, this transmission gate can amplifying signal, increases the susceptibility of bias voltage temperature instability test.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (15)
1. a bias voltage temperature instability test circuit, comprising:
Annular is reverberated device circuit, described ring oscillator circuit comprises n level test circuit, the structure of every grade of test circuit is identical, each test circuit comprises first node, Section Point and the 3rd node, the first node of each test circuit is connected with the 3rd node of its last test circuit, and n is positive integer; Wherein
Each test circuit comprises complementary PMOS pipe to be measured and NMOS to be measured pipe, complementary switch P metal-oxide-semiconductor and switch NMOS pipe and at least one pair of complementary dividing potential drop PMOS pipe and dividing potential drop NMOS pipe, and the source electrode of described PMOS pipe to be measured connects the first voltage end, grid connects first node, the source electrode of described NMOS pipe to be measured connects low level, grid connects first node, the source electrode of described switch P metal-oxide-semiconductor connects the first voltage end, grid connects second voltage end, drain electrode connects the 3rd node, the source electrode of described switch NMOS pipe connects low level end, grid connects tertiary voltage end, grounded drain the 3rd node, the drain electrode of described dividing potential drop PMOS pipe connects Section Point, grid connects the 4th voltage end, source electrode connects the drain electrode of described PMOS pipe to be measured, the drain electrode of described dividing potential drop NMOS pipe connects Section Point, grid connects the 5th voltage end, source electrode connects the drain electrode of described NMOS pipe to be measured.
2. bias voltage temperature instability test circuit as claimed in claim 1, is characterized in that, between the 3rd node of described each test circuit and the first node of its next test circuit, accesses a transmission gate.
3. bias voltage temperature instability test circuit as claimed in claim 2, is characterized in that, what described transmission gate was a pair of complementation puts big pmos and amplify NMOS pipe.
4. bias voltage temperature instability test circuit as claimed in claim 3, is characterized in that, described in put the grid of big pmos and the grid of described amplification NMOS pipe connects the 6th voltage end.
5. the bias voltage temperature instability test circuit as described in any one in claim 1-4, is characterized in that n >=3.
6. a method of testing for bias voltage temperature instability test circuit, comprising:
Bias voltage temperature instability test circuit is as claimed in claim 1 provided;
Test the Negative Bias Temperature Instability of PMOS pipe to be measured;
Test the positive bias temperature instability of NMOS pipe to be measured.
7. the method for testing of bias voltage temperature instability test circuit as claimed in claim 6, is characterized in that, the Negative Bias Temperature Instability of described test PMOS pipe to be measured comprises:
PMOS pipe to be measured is in pressure state, and described the first voltage end, second voltage end and the 4th voltage end are stress voltage, and tertiary voltage end is operating voltage, the 5th voltage end ground connection, and first node connects low level;
PMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end and the 5th voltage end are operating voltage, tertiary voltage end ground connection, described the 4th voltage end ground connection.
8. the method for testing of bias voltage temperature instability test circuit as claimed in claim 6, is characterized in that, the positive bias temperature instability of described test NMOS pipe to be measured comprises:
NMOS pipe to be measured is in pressure state, and described the first voltage end and the 4th voltage end are stress voltage, second voltage end, tertiary voltage end and the 5th voltage end ground connection, and first node connects stress voltage;
NMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end and the 5th voltage end are operating voltage, tertiary voltage end and the 4th voltage end ground connection.
9. the method for testing of the bias voltage temperature instability test circuit as described in any one in claim 6-8, is characterized in that, described stress voltage is greater than described operating voltage.
10. the method for testing of the bias voltage temperature instability test circuit as described in any one in claim 6-8, it is characterized in that, the variation that described bias voltage temperature instability is reverberated device circuit oscillation frequency by annular characterizes, or by annular, reverberates the curent change of PMOS to be measured pipe and NMOS pipe to be measured in device circuit and characterize.
The method of testing of 11. 1 kinds of bias voltage temperature instability test circuits, comprising:
Bias voltage temperature instability test circuit is as claimed in claim 1 provided;
Between the 3rd node of described each test circuit and the first node of its next test circuit, access a transmission gate, described transmission gate is putting big pmos and amplifying NMOS pipe of a pair of complementation, described in put the grid of big pmos and the grid of described amplification NMOS pipe connects the 6th voltage end;
Test the Negative Bias Temperature Instability of PMOS pipe to be measured;
Test the positive bias temperature instability of NMOS pipe to be measured.
The method of testing of 12. bias voltage temperature instability test circuits as claimed in claim 11, is characterized in that, the Negative Bias Temperature Instability of described test PMOS pipe to be measured comprises:
PMOS pipe to be measured is in pressure state, and described the first voltage end and the 4th voltage end second voltage end are stress voltage, and tertiary voltage end and the 6th voltage end are operating voltage, the 5th voltage end ground connection, and first node connects low level;
PMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end and the 5th voltage end are operating voltage, tertiary voltage end, the 4th voltage end and the 6th voltage end ground connection.
The method of testing of 13. bias voltage temperature instability test circuits as claimed in claim 11, is characterized in that, the positive bias temperature instability of described test NMOS pipe to be measured comprises:
NMOS pipe to be measured is in pressure state, and described the first voltage end and the 4th voltage end are stress voltage, second voltage end, tertiary voltage end and the 5th voltage end ground connection, and the 6th voltage end is operating voltage, first node connects stress voltage;
NMOS pipe to be measured is in test mode, and described the first voltage end, second voltage end, the 5th voltage end and the 6th voltage end are operating voltage, tertiary voltage end and the 4th voltage end ground connection.
The method of testing of 14. bias voltage temperature instability test circuits as described in any one in claim 11-13, is characterized in that, described stress voltage is greater than described operating voltage.
The method of testing of 15. bias voltage temperature instability test circuits as described in any one in claim 11-13, it is characterized in that, the variation that described bias voltage temperature instability is reverberated device circuit oscillation frequency by annular characterizes, or by annular, reverberates the curent change of PMOS to be measured pipe and NMOS pipe to be measured in device circuit and characterize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210264937.0A CN103576067A (en) | 2012-07-27 | 2012-07-27 | Bias voltage temperature instability testing circuit and testing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210264937.0A CN103576067A (en) | 2012-07-27 | 2012-07-27 | Bias voltage temperature instability testing circuit and testing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103576067A true CN103576067A (en) | 2014-02-12 |
Family
ID=50048261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210264937.0A Pending CN103576067A (en) | 2012-07-27 | 2012-07-27 | Bias voltage temperature instability testing circuit and testing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103576067A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483611A (en) * | 2014-11-24 | 2015-04-01 | 华东师范大学 | Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device |
| CN110988639A (en) * | 2019-11-08 | 2020-04-10 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method and device for testing stress bias temperature instability of constant electric field |
| CN113176482A (en) * | 2020-01-08 | 2021-07-27 | 中芯国际集成电路制造（天津）有限公司 | Test circuit, test system and test method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090189703A1 (en) * | 2008-01-29 | 2009-07-30 | International Business Machines Corporation | Circuits and design structures for monitoring nbti (negative bias temperature instability) effect and/or pbti (positive bias temperature instability) effect |
| US20090201055A1 (en) * | 2008-02-12 | 2009-08-13 | Sony Computer Entertainment Inc. | Methods and Apparatus For Managing LSI Power Consumption and Degradation Using Clock Signal Conditioning |
| US20100231258A1 (en) * | 2009-03-13 | 2010-09-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| US20110074394A1 (en) * | 2008-06-19 | 2011-03-31 | International Business Machines Corporation | Test circuit for bias temperature instability recovery measurements |
| CN102495352A (en) * | 2011-12-27 | 2012-06-13 | 复旦大学 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
| CN102543955A (en) * | 2010-12-08 | 2012-07-04 | 无锡华润上华科技有限公司 | Wafer-level negative bias temperature instability (NBTI) test structure |
| CN102590735A (en) * | 2012-02-16 | 2012-07-18 | 复旦大学 | Circuit and method for testing reliability of integrated circuit |
| US20120182079A1 (en) * | 2011-01-19 | 2012-07-19 | International Business Machines Corporation | Monitoring negative bias temperature instability (nbti) and/or positive bias temperature instability (pbti) |
-
2012
- 2012-07-27 CN CN201210264937.0A patent/CN103576067A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090189703A1 (en) * | 2008-01-29 | 2009-07-30 | International Business Machines Corporation | Circuits and design structures for monitoring nbti (negative bias temperature instability) effect and/or pbti (positive bias temperature instability) effect |
| US20090201055A1 (en) * | 2008-02-12 | 2009-08-13 | Sony Computer Entertainment Inc. | Methods and Apparatus For Managing LSI Power Consumption and Degradation Using Clock Signal Conditioning |
| US20110074394A1 (en) * | 2008-06-19 | 2011-03-31 | International Business Machines Corporation | Test circuit for bias temperature instability recovery measurements |
| US20100231258A1 (en) * | 2009-03-13 | 2010-09-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| CN102543955A (en) * | 2010-12-08 | 2012-07-04 | 无锡华润上华科技有限公司 | Wafer-level negative bias temperature instability (NBTI) test structure |
| US20120182079A1 (en) * | 2011-01-19 | 2012-07-19 | International Business Machines Corporation | Monitoring negative bias temperature instability (nbti) and/or positive bias temperature instability (pbti) |
| CN102495352A (en) * | 2011-12-27 | 2012-06-13 | 复旦大学 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
| CN102590735A (en) * | 2012-02-16 | 2012-07-18 | 复旦大学 | Circuit and method for testing reliability of integrated circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483611A (en) * | 2014-11-24 | 2015-04-01 | 华东师范大学 | Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device |
| CN104483611B (en) * | 2014-11-24 | 2017-05-24 | 华东师范大学 | Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device |
| CN110988639A (en) * | 2019-11-08 | 2020-04-10 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method and device for testing stress bias temperature instability of constant electric field |
| CN110988639B (en) * | 2019-11-08 | 2022-05-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method and device for testing stress bias temperature instability of constant electric field |
| CN113176482A (en) * | 2020-01-08 | 2021-07-27 | 中芯国际集成电路制造（天津）有限公司 | Test circuit, test system and test method thereof |
| CN113176482B (en) * | 2020-01-08 | 2023-03-07 | 中芯国际集成电路制造（天津）有限公司 | Test circuit, test system and test method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9671457B2 (en) | 3D IC testing apparatus | |
| CN102590735B (en) | Circuit and method for testing reliability of integrated circuit | |
| CN103091526B (en) | Voltage detection circuit | |
| CN102130668A (en) | Time-delay circuit | |
| CN103163444A (en) | Oscillation circuit and test circuit | |
| CN102866340A (en) | Building-out circuit and testing method for testing negative bias temperature instability | |
| CN103576067A (en) | Bias voltage temperature instability testing circuit and testing method thereof | |
| CN104483611A (en) | Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device | |
| JP2017174116A (en) | Voltage Regulator | |
| KR100714270B1 (en) | Charge pump in semiconductor memory device | |
| CN107889525A (en) | Ring oscillator hookup | |
| Iizuka et al. | All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter | |
| ATE543214T1 (en) | TEST STRUCTURE OF A MOS CAPACITOR AND METHOD OF MEASUREMENT OF A CAPACITY CURVE IN FUNCTION OF THE CORRESPONDING VOLTAGE | |
| CN103792475A (en) | Negative-bias-temperature-instability detection circuit and detection method thereof | |
| US10996261B2 (en) | Sensor for gate leakage detection | |
| CN203631540U (en) | Testing structure | |
| CN104931759B (en) | A kind of test circuit and test method of standard block leakage current | |
| CN106505980A (en) | Voltage detection circuit and electrification reset circuit | |
| US8729954B2 (en) | MOFSET mismatch characterization circuit | |
| US20120075937A1 (en) | Semiconductor Memory Device | |
| US20080191798A1 (en) | Bootstrap voltage generating circuits | |
| CN104700901B (en) | The detection method of memory cell in SRAM | |
| CN203811768U (en) | Hot carrier testing circuit | |
| CN102759697B (en) | Method for testing package level of metal oxide semiconductor (MOS) transistor and MOS transistor manufacturing method | |
| US20230021184A1 (en) | Test circuit, test method and memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140212 |