CN103424684A - Bias voltage temperature instability detection circuit and detection method - Google Patents
Bias voltage temperature instability detection circuit and detection method Download PDFInfo
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- CN103424684A CN103424684A CN2012101649956A CN201210164995A CN103424684A CN 103424684 A CN103424684 A CN 103424684A CN 2012101649956 A CN2012101649956 A CN 2012101649956A CN 201210164995 A CN201210164995 A CN 201210164995A CN 103424684 A CN103424684 A CN 103424684A
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Abstract
The invention provides bias voltage temperature instability detection circuit and detection method. The bias voltage temperature instability detection circuit comprises an odd number of fundamental oscillation units. Each fundamental oscillation unit comprises a first transistor, a second transistor, a first control transistor, a second control transistor, an input end and an output end. The detection circuit further comprises third transistors which are located between adjacent fundamental oscillation units. The fundamental oscillation units and the third transistors are connected in series to form an annular oscillator. According to the embodiment of the invention, the bias voltage temperature instability detection circuit can respectively detect the degree of threshold voltage degradation, which is caused by negative bias voltage temperature instability, of a PMOS transistor and the degree of threshold voltage degradation, which is caused by positive bias voltage temperature instability, of an NMOS transistor; by using the third transistors, the degree of threshold voltage degradation, which is caused by bias voltage temperature instability, of an MOS transistor can be amplified; and the final detection result is sensitive and the detection precision is high.
Description
Technical field
The present invention relates to the semiconductor detection technique, particularly a kind of testing circuit of bias voltage temperature instability and detection method.
Background technology
Along with the integrated level of SIC (semiconductor integrated circuit) is more and more higher, the requirement of transistor performance is also increased day by day, therefore, for the requirement of transistor reliability, improve thereupon.The bias voltage temperature instability of MOS transistor is the key factor that affects the MOS transistor reliability, and described bias voltage temperature instability comprises Negative Bias Temperature Instability and positive bias temperature instability.In existing CMOS technique, when being estimated for the transistorized reliability of PMOS, Negative Bias Temperature Instability is a main factor of evaluation.Negative Bias Temperature Instability refers to that the PMOS transistor is under the effect of negative bias grid voltage and high temperature, the hydrogen silicon bond rupture of the interface between the transistorized gate oxide of PMOS and substrate, form the boundary defect electric charge, thereby cause the transistorized threshold voltage of PMOS and saturated drain current that the phenomenon of drift occurs.
Along with constantly reducing of the design node of integrated circuit, utilize metal gates to replace the main direction that traditional polysilicon gate has become the microelectric technique development.The performance of metal gates can be subject to the impact of multiple charge defects, and wherein the oxygen vacancies of interstitial oxygen concentration atom and positively charged is very large on the instable impact of threshold voltage, thereby the electronics that they easily catch in high-K gate dielectric layer and Si produces the fast charging and discharging phenomenon.Adopt HfO
2With the contour K dielectric material of HfSiO, as the gate dielectric layer material, easily cause threshold voltage to be offset, utilize the nmos pass transistor of metal gates easily to be subject to the impact of positive bias temperature instability.Therefore, need the positive bias temperature instability of pair nmos transistor to be tested and analyze.
The american documentation literature that the patent No. is US7504847B2 discloses the instable method of testing of a kind of negative temperature bias voltage, specifically comprise: to being applied to stress device with voltage stress and the voltage on parametric device, be configured, and the gate source voltage of described parametric device is 0V, measure the source-drain current of described stress device and parametric device, judge that whether described stress device is because negative temperature bias voltage instability causes threshold voltage to be degenerated.But utilize the instable method of testing precision of described negative temperature bias voltage lower.
In other prior aries, also utilize the transistorized negative temperature bias voltage of ring oscillator test PMOS instability, please refer to Fig. 1, structural representation for the ring oscillator test circuit of prior art, described ring oscillator test circuit comprises the phase inverter 10,11,12 of three series connection, each phase inverter comprises a nmos pass transistor and a PMOS transistor, the transistorized end of described PMOS connects operating voltage Vdd, one end ground connection of described nmos pass transistor, described nmos pass transistor is connected with the output terminal of phase inverter with the transistorized other end of PMOS.Concrete method of testing comprises: disconnect the input end A1 of the phase inverter 10 in test circuit and the output terminals A 2 of phase inverter 12, input end A1 to phase inverter 10 applies low level, the transistorized grid of PMOS of described phase inverter 10, phase inverter 12 is subject to low level, and the PMOS transistor of described phase inverter 10, phase inverter 12 can produce because negative temperature bias voltage instability causes threshold voltage to be degenerated; The output terminals A 2 of the input end A1 of the phase inverter 10 in test circuit and phase inverter 12 is connected, the phase inverter 10,11,12 of three series connection forms ring oscillator, by detect input end A1 is applied to low level before and oscillation frequency that input end A1 is applied to the ring oscillator after low level, utilize both oscillation frequency rate variances to judge that whether the PMOS transistor of described phase inverter 10, phase inverter 12 is because negative temperature bias voltage instability causes threshold voltage to be degenerated.But along with the nmos pass transistor with metal gates is more and more general, when the transistorized grid structure of the nmos pass transistor in described phase inverter and PMOS is metal gates, input end A1 to phase inverter 10 applies low level, the grid of the nmos pass transistor of described phase inverter 11 can be subject to high level, the nmos pass transistor of described phase inverter 11 also can cause threshold voltage to be degenerated because of positive temperature bias instability, both can final oscillation frequency be impacted, make and can not judge according to final oscillation frequency rate variance described phase inverter 10, the PMOS transistor of phase inverter 12 is because the degree that negative temperature bias voltage instability causes threshold voltage to be degenerated.
Summary of the invention
The problem that the present invention solves is to provide testing circuit and the detection method of a kind of high precision and bias voltage temperature instability that can independent detection.
For addressing the above problem, technical solution of the present invention provides a kind of testing circuit of bias voltage temperature instability, comprising:
Odd number fundamental oscillation unit, described fundamental oscillation unit comprises the first transistor, transistor seconds and the first control transistor, the second control transistor, input end, output terminal, and described the first transistor, first is controlled the type of transistorized channel region and the type opposite that transistor seconds, second is controlled transistorized channel region;
The grid of described the first transistor and transistor seconds is connected with input end, and described the first control transistor and second is controlled transistorized grid and is connected with control voltage end electricity,
The first end of described the first transistor, first is controlled transistorized first end and is connected with the first voltage end electricity, and the second end of described the first transistor, first is controlled transistorized the second end and is connected with output terminal electricity,
The first end of described transistor seconds is connected with second voltage end electricity, and the second end of described transistor seconds and second is controlled transistorized first end electricity and is connected, and described second controls transistorized the second end is connected with output terminal electricity;
The 3rd transistor between described adjacent fundamental oscillation unit, described the 3rd transistorized grid is connected with tertiary voltage end electricity, described the 3rd transistorized first end is connected with the output terminal electricity of one of them fundamental oscillation unit, the described the 3rd transistorized the second end is connected with the input end electricity of another fundamental oscillation unit, and described fundamental oscillation unit and the 3rd transistor series form ring oscillator.
Optionally, the type of described the 3rd transistorized channel region is identical with the type of the channel region of transistor seconds.
Optionally, utilize described tertiary voltage end to make the 3rd transistorized channel region open.
Optionally, it is the PMOS transistor that described the first transistor, first is controlled transistor, it is nmos pass transistor that described transistor seconds, second is controlled transistor, and the voltage of described the first voltage end is operating voltage, and the voltage of described second voltage end is no-voltage or negative bias.
Optionally, the grid of described transistor seconds is metal gates.
Optionally, it is nmos pass transistor that described the first transistor, first is controlled transistor, it is the PMOS transistor that described transistor seconds, second is controlled transistor, and the voltage of described second voltage end is operating voltage, and the voltage of described the first voltage end is no-voltage or negative bias.
Optionally, the grid of described transistor seconds is metal gates or polysilicon gate.
Optionally, described PMOS transistor is enhancement mode PMOS transistor or depletion type PMOS transistor, and described nmos pass transistor is enhancement mode nmos pass transistor or depletion type nmos transistor.
Optionally, utilizing described control voltage end to control first controls transistorized channel region and the transistorized channel region unlatching of the second control or closes.
Technical solution of the present invention also provides a kind of detection method that adopts the testing circuit of described bias voltage temperature instability, comprising:
Applying the first control voltage at described control voltage end makes the transistorized channel region of the first control open, second controls transistorized channel region closes, make the grid of transistor seconds be applied with bias voltage, transistor seconds is because the bias voltage temperature instability causes threshold voltage to be degenerated;
Apply the second control voltage at described control voltage end and make the transistorized channel region of the second control open, first controls transistorized channel region closes, described ring oscillator normal operation, and the detection frequency of detection ring oscillator;
According to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that the bias voltage temperature instability causes threshold voltage to be degenerated.
Optionally, the detection frequency of described ring oscillator and the difference DELTA f=k between standard frequency
PΔ V
THP+ k
NΔ V
THN+ k
LΔ L, wherein said Δ V
THPFor the changing value of the transistorized threshold voltage of PMOS in the first transistor and transistor seconds, described Δ V
THNFor the changing value of the threshold voltage of nmos pass transistor in the first transistor and transistor seconds, the changing value that Δ L is the length of channel region in MOS transistor, described k
P, k
N, k
LFor constant.
Optionally, when described the first transistor, the first control transistor is the PMOS transistor, described transistor seconds, the second control transistor is nmos pass transistor, the voltage of described the first voltage end is operating voltage, the voltage of described second voltage end is no-voltage or negative bias, described the first control voltage is no-voltage or negative voltage, when described the second control voltage is operating voltage, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal operating voltage, make the grid of the first transistor and transistor seconds be applied with operating voltage, make transistor seconds because the positive bias temperature instability causes threshold voltage to be degenerated, and according to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that the positive bias temperature instability causes threshold voltage to be degenerated.
Optionally, when described the first transistor, the first control transistor is nmos pass transistor, described transistor seconds, the second control transistor is the PMOS transistor, the voltage of described second voltage end is operating voltage, the voltage of described the first voltage end is no-voltage or negative bias, described the first control voltage is operating voltage, when described the second control voltage is no-voltage or negative voltage, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal zero voltage or negative bias, make the grid of the first transistor and transistor seconds be applied with no-voltage or negative bias, make transistor seconds because Negative Bias Temperature Instability causes threshold voltage to be degenerated, and according to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that Negative Bias Temperature Instability causes threshold voltage to be degenerated.
Compared with prior art, the present invention has the following advantages:
The testing circuit of the bias voltage temperature instability of the embodiment of the present invention comprises odd number fundamental oscillation unit and the 3rd transistor between described adjacent fundamental oscillation unit, and described fundamental oscillation unit comprises that the first transistor, transistor seconds and first control transistor, second and control transistor, input end, output terminal, the grid of described the first transistor and transistor seconds is connected with input end, described the first control transistor and second is controlled transistorized grid and is connected with control voltage end electricity, the first end of described the first transistor, first controls transistorized first end is connected with the first voltage end electricity, the second end of described the first transistor, first controls transistorized the second end is connected with output terminal electricity, the first end of described transistor seconds is connected with second voltage end electricity, the second end of described transistor seconds and second is controlled transistorized first end electricity and is connected, described second controls transistorized the second end is connected with output terminal electricity, owing to utilizing ring oscillator that described fundamental oscillation unit forms can detect separately PMOS transistor or nmos pass transistor because the bias voltage temperature instability causes threshold voltage that the degree of degenerating occurs, can not interfere with each other, and utilize described the 3rd transistor, can cause the degree of threshold voltage degeneration because of the temperature bias instability by amplifying mos transistor, make testing result sensitiveer, the precision detected is higher.
Further, when the type of described the 3rd transistorized channel region is identical with the type of the channel region of transistor seconds, be all the PMOS transistor or be all nmos pass transistor, amplification detection result by a larger margin, the precision of detection is higher.
The accompanying drawing explanation
Fig. 1 is the structural representation of the ring oscillator test circuit of prior art;
The structural representation of the testing circuit of the bias voltage temperature instability that Fig. 2 is first embodiment of the invention;
Fig. 3 is the schematic flow sheet of the detection method of the testing circuit of the bias voltage temperature instability of employing first embodiment of the invention;
The structural representation of the testing circuit of the bias voltage temperature instability that Fig. 4 is second embodiment of the invention;
Fig. 5 is the schematic flow sheet of the detection method of the testing circuit of the bias voltage temperature instability of employing second embodiment of the invention.
Embodiment
Because prior art is lower to the instable method of testing of negative temperature bias voltage or precision, perhaps when the grid of MOS transistor to be tested is metal gates, can not effectively test because the degree that negative temperature bias voltage instability causes threshold voltage to be degenerated, the inventor is through research, a kind of testing circuit and detection method of bias voltage temperature instability have been proposed, the testing circuit of described bias voltage temperature instability comprises: odd number fundamental oscillation unit, described fundamental oscillation unit comprises the first transistor, transistor seconds and first is controlled transistor, second controls transistor, input end, output terminal, the grid of described the first transistor and transistor seconds is connected with input end, described the first control transistor and second is controlled transistorized grid and is connected with control voltage end electricity, the first end of described the first transistor, first controls transistorized first end is connected with the first voltage end electricity, the second end of described the first transistor, first controls transistorized the second end is connected with output terminal electricity, the first end of described transistor seconds is connected with second voltage end electricity, the second end of described transistor seconds and second is controlled transistorized first end electricity and is connected, described second controls transistorized the second end is connected with output terminal electricity, the 3rd transistor between described adjacent fundamental oscillation unit, described the 3rd transistorized grid is connected with tertiary voltage end electricity, described the 3rd transistorized first end is connected with the output terminal electricity of one of them fundamental oscillation unit, the described the 3rd transistorized the second end is connected with the input end electricity of another fundamental oscillation unit, and described fundamental oscillation unit and the 3rd transistor series form ring oscillator.
Utilize the testing circuit of the bias voltage temperature instability of the embodiment of the present invention, controlling transistor when described the first transistor, first is the PMOS transistor, it is nmos pass transistor that described transistor seconds, second is controlled transistor, can detect nmos pass transistor because the degree that the threshold voltage that the positive bias temperature instability causes is degenerated; Controlling transistor when described the first transistor, first is nmos pass transistor, it is the PMOS transistor that described transistor seconds, second is controlled transistor, can detect the PMOS transistor because the degree that the threshold voltage that Negative Bias Temperature Instability causes is degenerated, and utilize the 3rd transistor, can amplifying mos transistor because the degree that the threshold voltage that the bias voltage temperature instability causes is degenerated, make final testing result sensitiveer, the precision of detection is higher.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
The first embodiment
At first first embodiment of the invention provides a kind of testing circuit of the temperature instability of the positive bias for detection of nmos pass transistor, please refer to Fig. 2, and the structural representation for the testing circuit of the bias voltage temperature instability of the embodiment of the present invention specifically comprises:
The fundamental oscillation unit 210 that the odd number circuit structure is identical, wherein fundamental oscillation unit 210 comprises the first transistor 211, transistor seconds 212 and the first control transistor 213, the second control transistor 214, input end 215, output terminal 216, it is the PMOS transistor that described the first transistor 211, first is controlled transistor 213, and it is nmos pass transistor that described transistor seconds 212, second is controlled transistor 214;
The grid of described the first transistor 211 and transistor seconds 212 is connected with input end 215, and the described first grid of controlling transistor 213 and the second control transistor 214 is connected with control voltage end 240 electricity,
The first end of described the first transistor 211, the first first end of controlling transistor 213 are connected with the first voltage end 250 electricity, and the second end of described the first transistor 211, first the second end of controlling transistor 213 are connected with output terminal 216 electricity,
The first end of described transistor seconds 212 is connected with second voltage end 260 electricity, the second end of described transistor seconds 212 is connected with the second first end electricity of controlling transistor 214, and described second the second end of controlling transistor 214 is connected with output terminal 216 electricity;
The 3rd transistor 220 between described adjacent fundamental oscillation unit 210, described the 3rd transistor 220 is nmos pass transistor, the grid of described the 3rd transistor 220 is connected with tertiary voltage end 230 electricity, the first end of described the 3rd transistor 220 is connected with output terminal 216 electricity of one of them fundamental oscillation unit, the second end of described the 3rd transistor 220 is connected with input end 215 electricity of another fundamental oscillation unit, and described fundamental oscillation unit 210 and the 3rd transistor 220 series connection form ring oscillator.
Concrete, in Fig. 2, the testing circuit of described bias voltage temperature instability comprises 3 fundamental oscillation unit 210 and the 3rd transistor 220 that is positioned at adjacent two fundamental oscillation unit 210 that circuit structure is identical, described fundamental oscillation unit 210, the 3rd transistor 220 series connection and end to end.In other embodiment, the testing circuit of described bias voltage temperature instability comprises the identical fundamental oscillation unit and the 3rd transistor that is positioned at adjacent two fundamental oscillation unit, described fundamental oscillation unit, the 3rd transistor series and end to end of odd number circuit structure that is greater than 3.
Described the first transistor 211, transistor seconds 212 and first are controlled transistor 213, the second first end of controlling in transistor 214, the 3rd transistor 220 is the source electrode in MOS transistor or drains one of them, and described the first transistor 211, transistor seconds 212 and first are controlled transistor 213, second to control the second end in transistor 214, the 3rd transistor 220 be wherein another of source electrode in MOS transistor or drain electrode.
In the present embodiment, it is depletion type PMOS transistor that described the first transistor 211, first is controlled transistor 213, and it is the enhancement mode nmos pass transistor that described transistor seconds 212, second is controlled transistor 214.The voltage that described the first voltage end 250 applies is operating voltage, and described operating voltage is 1V, 1.2V, 1.5V or 1.8V etc.The voltage that described the first voltage end applies is corresponding to the noble potential of ring oscillator.Described second voltage end 260 ground connection, the voltage of described second voltage end 260 is no-voltage.In other embodiments, the voltage of described second voltage end 260 can also be negative voltage.The voltage of described second voltage end is corresponding to the electronegative potential of ring oscillator.The voltage that described control voltage end 240 applies comprises operating voltage or no-voltage, when controlling voltage that voltage end 240 applies and be operating voltage, the first channel region of controlling transistor 213 is closed, the second channel region of controlling transistor 214 is opened, the voltage applied when described control voltage end 240 is no-voltage, the first channel region of controlling transistor 213 is opened, and the second channel region of controlling transistor 214 is closed.Described the 3rd transistor 220 is nmos pass transistor, can be enhancement mode nmos pass transistor or depletion type nmos transistor, the voltage that described tertiary voltage end 230 applies is operating voltage, described operating voltage is 1V, 1.2V, 1.5V or 1.8V etc., makes the channel region of described the 3rd transistor 220 in opening.
In other embodiments, it can also be enhancement mode PMOS transistor that described the first transistor 211, first is controlled transistor 213, and it can also be depletion type nmos transistor that described transistor seconds 212, second is controlled transistor 214.By configuring the first voltage end, the second voltage end, the tertiary voltage end, control the voltage of voltage end, make the high level of the voltage of described the first voltage end corresponding to ring oscillator, the voltage of described second voltage end is corresponding to the low level of ring oscillator, described tertiary voltage end can be controlled the transistorized channel region of the first control simultaneously and close, second controls transistorized channel region opens, or control the transistorized channel region of the first control simultaneously and close, second controls transistorized channel region opens, the voltage of described tertiary voltage end makes the 3rd transistorized channel region in opening.
The testing circuit of the bias voltage temperature instability of the present embodiment is for detection of the positive bias temperature instability of described transistor seconds 212, and the grid of described transistor seconds 212 is metal gates.Because the nmos pass transistor with metal gates easily is subject to the impact of positive bias temperature instability, therefore, the grid of the transistor seconds 212 of the embodiment of the present invention is metal gates.
In embodiments of the present invention, described the 3rd transistor 220 is nmos pass transistor, and in other embodiments, described the 3rd transistor can be also the PMOS transistor.
First embodiment of the invention also provides a kind of detection method that adopts the testing circuit of described bias voltage temperature instability, please refer to Fig. 3, and the schematic flow sheet for the testing process of the testing circuit that adopts described bias voltage temperature instability specifically comprises:
Step S101, applying the first control voltage at described control voltage end makes the transistorized channel region of the first control open, second controls transistorized channel region closes, make the output terminal of fundamental oscillation unit and the voltage of input end equal operating voltage, make the grid of the first transistor and transistor seconds be applied with operating voltage, make transistor seconds because the positive bias temperature instability causes threshold voltage to be degenerated;
Step S102, apply the second control voltage at described control voltage end and make the transistorized channel region of the second control open, and first controls transistorized channel region closes, described ring oscillator normal operation, and the detection frequency of detection ring oscillator;
Step S103, according to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that the positive bias temperature instability causes threshold voltage to be degenerated.
Concrete, please refer to Fig. 2, apply the first control voltage at described control voltage end 240, described the first control voltage is no-voltage, be described control voltage end 240 ground connection, make the channel region of the first control transistor 213 open, the second channel region of controlling transistor 214 is closed, the voltage of output terminal 216 is approximately equal to the operating voltage on the first voltage end 250, and due to the channel region of the 3rd transistor 220 in opening, make the voltage of the input end 215 of next fundamental oscillation unit also be approximately operating voltage, make the first transistor 211 in each fundamental oscillation unit and the grid of transistor seconds 212 be applied with operating voltage.Because described the first transistor 211 is the PMOS transistor, described transistor seconds 212 is nmos pass transistor, the grid of nmos pass transistor is subject to positive voltage for a long time can be because the positive bias temperature instability causes threshold voltage to be degenerated, cause threshold voltage and saturated drain current to be drifted about, and the time absolute value longer, positive voltage that is subject to positive voltage along with grid is larger, easier because the positive bias temperature instability causes threshold voltage to be degenerated.Therefore, need pair nmos transistor because the degree that the positive bias temperature instability causes threshold voltage to occur to degenerate is detected.
Please refer to Fig. 2, apply the second control voltage at described control voltage end 240, described the second control voltage is operating voltage, such as 1V, 1.2V, 1.5V or 1.8V etc., make the channel region of the first control transistor 213 close, the second channel region of controlling transistor 214 is opened, and the second end of described transistor seconds 212 is connected with output terminal 216 electricity, and described the first transistor 211, transistor seconds 212 form the phase inverter of a ring oscillator as shown in Figure 1.Input end input high level when one of them fundamental oscillation unit 210, operating voltage for example, a low level of input end input of next fundamental oscillation unit 210, no-voltage for example, because the quantity of the fundamental oscillation unit 210 of ring oscillator is odd number, thereby cause vibration, and detect the detection frequency of ring oscillator when vibrational stabilization.Owing to forming the first transistor 211 of phase inverter in the present embodiment, in transistor seconds 212, only have transistor seconds 212 to be subject to the bias voltage temperature instability, therefore the oscillation frequency of ring oscillator to change be mainly by transistor seconds 212(NMOS transistor) be subject to threshold voltage that the positive bias temperature instability causes and source-drain current and change and cause, do not have other factors to disturb, thereby the degree that can change by the oscillation frequency of ring oscillator judgement nmos pass transistor is because the positive bias temperature instability causes threshold voltage that the degree of degenerating occurs.
Because the described detection frequency recorded is to record when the threshold voltage of transistor seconds 212 occurs to degenerate, the standard frequency that described detection frequency records while degenerating with the threshold voltage of transistor seconds 212 is compared and is had certain difference, the inventor finds through research, the detection frequency of described ring oscillator and the difference DELTA f=k between standard frequency
PΔ V
THP+ k
NΔ V
THN+ k
LΔ L, wherein said Δ V
THPFor the changing value of the transistorized threshold voltage of PMOS in the first transistor and transistor seconds, described Δ V
THNFor the changing value of the threshold voltage of nmos pass transistor in the first transistor and transistor seconds, the changing value that Δ L is the length of channel region in MOS transistor, described k
P, k
N, k
LFor constant, relevant to the circuit structure of ring oscillator, and along with the increase of fundamental oscillation element number, described k
P, k
N, k
LAlso can increase thereupon.
The inventor also finds through research, add a MOS transistor between every two fundamental oscillation circuit of ring oscillator, a wherein end in the source-drain electrode of described MOS transistor is connected with the output terminal of a fundamental oscillation circuit, wherein the other end is connected with the input end of another fundamental oscillation circuit, utilize described MOS transistor, can be so that k
P, k
N, k
LThe absolute value of three constants increases, can be so that the difference between the detection frequency of described ring oscillator and standard frequency increases, can amplify nmos pass transistor because the degree that the threshold voltage that the positive bias temperature instability causes is degenerated, make final testing result sensitiveer, the precision of detection is higher.Please refer to table 1, is the k that the 3rd transistorized ring oscillator is corresponding with there is no the 3rd transistorized ring oscillator that has of the embodiment of the present invention
P, k
N, k
LThe comparison sheet of three constants.
| The ring oscillator type | k P | k N | k L |
| There is no the 3rd transistor | -0.038 | -0.035 | -0.026 |
| The 3rd transistor is the PMOS transistor | -0.24 | -0.052 | -0.085 |
| The 3rd transistor is nmos pass transistor | -0.054 | -0.34 | -0.029 |
Table 1
As seen from the table, add a MOS transistor between every two fundamental oscillation circuit of ring oscillator and can obviously improve k
P, k
NThe absolute value of these two constants, and can be so that the difference DELTA f between the detection frequency of described ring oscillator and standard frequency increases, can amplifying mos transistor because the degree that the threshold voltage that the bias voltage temperature instability causes is degenerated, make final testing result sensitiveer, the precision of detection is higher.
Owing to working as described k
P, k
N, k
LDuring three determination of the constants, in the changing value of the changing value of the main and transistorized threshold voltage of PMOS of the difference between the detection frequency of described ring oscillator and standard frequency, the threshold voltage of nmos pass transistor, MOS transistor, the length of grid is relevant, transistor seconds 212(NMOS transistor in the embodiment of the present invention) impact that threshold voltage easily is subject to the positive bias temperature instability changes, and in the transistorized threshold voltage of PMOS, MOS transistor, the length of channel region can not change, therefore in the present embodiment, Δ f ≈ k
NΔ V
THN.Corresponding k owing to there is no the 3rd transistor
NFor-0.035, and there is the 3rd transistor and the 3rd transistor corresponding k while being nmos pass transistor
NFor-0.34, can improve greatly the detection frequency of described ring oscillator and the difference DELTA f between standard frequency, can amplify nmos pass transistor because the degree that the threshold voltage that the positive bias temperature instability causes is degenerated.Corresponding k while in other embodiments, due to the 3rd transistor, being the PMOS transistor
NFor-0.052, be k corresponding while there is no the 3rd transistor
NBe worth 1.5 times, also can amplify nmos pass transistor because the degree that the threshold voltage that the positive bias temperature instability causes is degenerated.
Detection frequency by recording described ring oscillator and the difference between standard frequency, just the changing value of the threshold voltage of nmos pass transistor can be obtained, thereby the nmos pass transistor of described transistor seconds can be judged because the degree that the threshold voltage that the positive bias temperature instability causes is degenerated.
The second embodiment
Second embodiment of the invention provides a kind of testing circuit for detection of the transistorized Negative Bias Temperature Instability of PMOS, please refer to Fig. 4, and the structural representation for the testing circuit of the bias voltage temperature instability of the embodiment of the present invention specifically comprises:
The fundamental oscillation unit 310 that the odd number circuit structure is identical, wherein fundamental oscillation unit 310 comprises the first transistor 311, transistor seconds 312 and the first control transistor 313, the second control transistor 314, input end 315, output terminal 316, it is nmos pass transistor that described the first transistor 311, first is controlled transistor 313, and it is the PMOS transistor that described transistor seconds 312, second is controlled transistor 314;
The grid of described the first transistor 311 and transistor seconds 312 is connected with input end 315, and the described first grid of controlling transistor 313 and the second control transistor 314 is connected with control voltage end 340 electricity,
The first end of described the first transistor 311, the first first end of controlling transistor 313 are connected with the first voltage end 350 electricity, and the second end of described the first transistor 311, first the second end of controlling transistor 313 are connected with output terminal 316 electricity,
The first end of described transistor seconds 312 is connected with second voltage end 360 electricity, the second end of described transistor seconds 312 is connected with the second first end electricity of controlling transistor 314, and described second the second end of controlling transistor 314 is connected with output terminal 316 electricity;
The 3rd transistor 320 between described adjacent fundamental oscillation unit 310, described the 3rd transistor 320 is the PMOS transistor, the grid of described the 3rd transistor 320 is connected with tertiary voltage end 330 electricity, the first end of described the 3rd transistor 320 is connected with output terminal 316 electricity of one of them fundamental oscillation unit, the second end of described the 3rd transistor 320 is connected with input end 315 electricity of another fundamental oscillation unit, and described fundamental oscillation unit 310 and the 3rd transistor 320 series connection form ring oscillator.
Concrete, in Fig. 4, the testing circuit of described bias voltage temperature instability comprises 3 fundamental oscillation unit 310 and the 3rd transistor 320 that is positioned at adjacent two fundamental oscillation unit 310 that circuit structure is identical, described fundamental oscillation unit 310, the 3rd transistor 320 series connection and end to end.In other embodiment, the testing circuit of described bias voltage temperature instability comprises the identical fundamental oscillation unit and the 3rd transistor that is positioned at adjacent two fundamental oscillation unit, described fundamental oscillation unit, the 3rd transistor series and end to end of odd number circuit structure that is greater than 3.
Described the first transistor 311, transistor seconds 312 and first are controlled transistor 313, the second first end of controlling in transistor 314, the 3rd transistor 320 is the source electrode in MOS transistor or drains one of them, and described the first transistor 311, transistor seconds 312 and first are controlled transistor 313, second to control the second end in transistor 314, the 3rd transistor 320 be wherein another of source electrode in MOS transistor or drain electrode.
In the present embodiment, it is the enhancement mode nmos pass transistor that described the first transistor 311, first is controlled transistor 313, and it is depletion type PMOS transistor that described transistor seconds 312, second is controlled transistor 314.The voltage that described second voltage end 360 applies is operating voltage, and described operating voltage is 1V, 1.2V, 1.5V or 1.8V etc.The voltage that described second voltage end applies is corresponding to the noble potential of ring oscillator.Described the first voltage end 350 ground connection, the voltage of described the first voltage end 350 is no-voltage.In other embodiments, the voltage of described the first voltage end 350 can also be negative voltage.The voltage of described the first voltage end is corresponding to the electronegative potential of ring oscillator.The voltage that described control voltage end 340 applies comprises operating voltage or no-voltage, when controlling voltage that voltage end 340 applies and be operating voltage, the first channel region of controlling transistor 313 is opened, the second channel region of controlling transistor 314 is closed, the voltage applied when described control voltage end 340 is no-voltage, the first channel region of controlling transistor 313 is closed, and the second channel region of controlling transistor 314 is opened.Described the 3rd transistor 320 is the PMOS transistor, can be enhancement mode PMOS transistor or depletion type PMOS transistor, and the voltage that described tertiary voltage end 330 applies is no-voltage or negative voltage, makes the channel region of described the 3rd transistor 320 in opening.
In other embodiments, it can also be depletion type nmos transistor that described the first transistor 311, first is controlled transistor 313, and it can also be enhancement mode PMOS transistor that described transistor seconds 312, second is controlled transistor 314.By configuring the first voltage end, the second voltage end, the tertiary voltage end, control the voltage of voltage end, make the low level of the voltage of described the first voltage end corresponding to ring oscillator, the voltage of described second voltage end is corresponding to the high level of ring oscillator, described tertiary voltage end can be controlled the transistorized channel region of the first control simultaneously and close, second controls transistorized channel region opens, or control the transistorized channel region of the first control simultaneously and close, second controls transistorized channel region opens, the voltage of described tertiary voltage end makes the 3rd transistorized channel region in opening.
The testing circuit of the bias voltage temperature instability of the present embodiment is for detection of the Negative Bias Temperature Instability of described transistor seconds 312, and the grid of described transistor seconds 312 is metal gates or polysilicon gate.Because the PMOS transistor with metal gates or polysilicon gate easily is subject to the impact of Negative Bias Temperature Instability, therefore, the grid of the transistor seconds 312 of the embodiment of the present invention is metal gates or polysilicon gate.
In embodiments of the present invention, described the 3rd transistor 320 is the PMOS transistor, and in other embodiments, described the 3rd transistor can be also nmos pass transistor.
Second embodiment of the invention also provides a kind of detection method that adopts the testing circuit of described bias voltage temperature instability, please refer to Fig. 5, and the schematic flow sheet for the testing process of the testing circuit that adopts described bias voltage temperature instability specifically comprises:
Step S201, applying the first control voltage at described control voltage end makes the transistorized channel region of the first control open, second controls transistorized channel region closes, make the voltage of the output terminal of fundamental oscillation unit and the input end voltage that equals zero, make the grid of the first transistor and transistor seconds be applied with no-voltage, make transistor seconds because Negative Bias Temperature Instability causes threshold voltage to be degenerated;
Step S202, apply the second control voltage at described control voltage end and make the transistorized channel region of the second control open, and first controls transistorized channel region closes, described ring oscillator normal operation, and the detection frequency of detection ring oscillator;
Step S203, according to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that Negative Bias Temperature Instability causes threshold voltage to be degenerated.
Concrete, please refer to Fig. 4, apply the first control voltage at described control voltage end 340, described the first control voltage is operating voltage, 1V for example, 1.2V, 1.5V or 1.8V etc., make the channel region of the first control transistor 313 open, the second channel region of controlling transistor 314 is closed, the voltage of output terminal 316 is approximately equal to the no-voltage on the first voltage end 350, and due to the channel region of the 3rd transistor 320 in opening, make the voltage of the input end 315 of next fundamental oscillation unit also be approximately no-voltage, make the first transistor 311 in each fundamental oscillation unit and the grid of transistor seconds 312 be applied with operating voltage.Because described the first transistor 311 is nmos pass transistor, described transistor seconds 312 is the PMOS transistor, the transistorized grid of PMOS is subject to negative bias for a long time can be because Negative Bias Temperature Instability causes threshold voltage to be degenerated, cause threshold voltage and saturated drain current to be drifted about, and the time absolute value longer, negative bias that is subject to negative bias along with grid is larger, easier because the positive bias temperature instability causes threshold voltage to be degenerated.Therefore, need pair pmos transistor because the degree that Negative Bias Temperature Instability causes threshold voltage to occur to degenerate is detected.
In other embodiments, voltage on described the first voltage end 350 is negative voltage, make the output terminal 316 of fundamental oscillation unit and the voltage of input end 315 equal negative voltage, make the grid of the first transistor 311 and transistor seconds 312 be applied with negative voltage, make grid be subject to larger negative bias, more easily make transistor seconds 312 because Negative Bias Temperature Instability causes threshold voltage to be degenerated.
Please refer to Fig. 4, apply the second control voltage at described control voltage end 340, described the second control voltage is no-voltage or negative voltage, make the channel region of the first control transistor 313 close, the second channel region of controlling transistor 314 is opened, the second end of described transistor seconds 312 is connected with output terminal 316 electricity, and described the first transistor 311, transistor seconds 312 form the phase inverter of a ring oscillator as shown in Figure 1.Input end input high level when one of them fundamental oscillation unit 310, operating voltage for example, a low level of input end input of next fundamental oscillation unit 310, no-voltage for example, because the quantity of the fundamental oscillation unit 210 of ring oscillator is odd number, thereby cause vibration, and detect the detection frequency of ring oscillator when vibrational stabilization.Owing to forming the first transistor 311 of phase inverter in the present embodiment, in transistor seconds 312, only have transistor seconds 312 to be subject to the bias voltage temperature instability, therefore the oscillation frequency of ring oscillator to change be mainly by transistor seconds 312(PMOS transistor) be subject to threshold voltage that Negative Bias Temperature Instability causes and source-drain current and change and cause, do not have other factors to disturb, thereby the degree that can change by the oscillation frequency of ring oscillator judgement PMOS transistor is because Negative Bias Temperature Instability causes threshold voltage that the degree of degenerating occurs.
Because the described detection frequency recorded is to record when the threshold voltage of transistor seconds 312 occurs to degenerate, the standard frequency that described detection frequency records while degenerating with the threshold voltage of transistor seconds 312 is compared, thereby can certain difference be arranged because the transistorized threshold voltage of PMOS occurs to degenerate.Due to the detection frequency of described ring oscillator and the difference DELTA f=k between standard frequency
PΔ V
THP+ k
NΔ V
THN+ k
LΔ L.Owing to working as described k
P, k
N, k
LDuring three determination of the constants, in the changing value of the changing value of the main and transistorized threshold voltage of PMOS of the difference between the detection frequency of described ring oscillator and standard frequency, the threshold voltage of nmos pass transistor, MOS transistor, the length of grid is relevant, transistor seconds 312(PMOS transistor in the embodiment of the present invention) impact that threshold voltage easily is subject to Negative Bias Temperature Instability changes, and in the threshold voltage of nmos pass transistor, MOS transistor, the length of channel region can not change, therefore in the present embodiment, Δ f ≈ k
PΔ V
THP.
Please refer to table 1, corresponding k owing to there is no the 3rd transistor
PFor-0.038, and there is the 3rd transistor and the 3rd transistor corresponding k while being the PMOS transistor
PFor-0.24, can improve greatly the detection frequency of described ring oscillator and the difference DELTA f between standard frequency, can amplify the PMOS transistor because the degree that the threshold voltage that Negative Bias Temperature Instability causes is degenerated makes final testing result sensitiveer, the precision of detection is higher.Corresponding k while in other embodiments, due to the 3rd transistor, being nmos pass transistor
NFor-0.054, be approximately k corresponding while there is no the 3rd transistor
N1.5 times of value, also can amplify the PMOS transistor because the degree that the threshold voltage that causes of Negative Bias Temperature Instability is degenerated.
Detection frequency by recording described ring oscillator and the difference between standard frequency, just the changing value of the transistorized threshold voltage of PMOS can be obtained, thereby the PMOS transistor of described transistor seconds can be judged because the degree that the threshold voltage that Negative Bias Temperature Instability causes is degenerated.
To sum up, the testing circuit of the bias voltage temperature instability of the embodiment of the present invention comprises odd number fundamental oscillation unit and the 3rd transistor between described adjacent fundamental oscillation unit, and described fundamental oscillation unit comprises that the first transistor, transistor seconds and first control transistor, second and control transistor, input end, output terminal, the grid of described the first transistor and transistor seconds is connected with input end, described the first control transistor and second is controlled transistorized grid and is connected with control voltage end electricity, the first end of described the first transistor, first controls transistorized first end is connected with the first voltage end electricity, the second end of described the first transistor, first controls transistorized the second end is connected with output terminal electricity, the first end of described transistor seconds is connected with second voltage end electricity, the second end of described transistor seconds and second is controlled transistorized first end electricity and is connected, described second controls transistorized the second end is connected with output terminal electricity, owing to utilizing ring oscillator that described fundamental oscillation unit forms can detect separately PMOS transistor or nmos pass transistor because the bias voltage temperature instability causes threshold voltage that the degree of degenerating occurs, can not interfere with each other, and utilize described the 3rd transistor, can cause the degree of threshold voltage degeneration because of the temperature bias instability by amplifying mos transistor, make testing result sensitiveer, the precision detected is higher.
Further, when the type of described the 3rd transistorized channel region is identical with the type of the channel region of transistor seconds, be all the PMOS transistor or be all nmos pass transistor, amplification detection result by a larger margin, the precision of detection is higher.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (13)
1. the testing circuit of a bias voltage temperature instability, is characterized in that, comprising:
Odd number fundamental oscillation unit, described fundamental oscillation unit comprises the first transistor, transistor seconds and the first control transistor, the second control transistor, input end, output terminal, and described the first transistor, first is controlled the type of transistorized channel region and the type opposite that transistor seconds, second is controlled transistorized channel region;
The grid of described the first transistor and transistor seconds is connected with input end, and described the first control transistor and second is controlled transistorized grid and is connected with control voltage end electricity,
The first end of described the first transistor, first is controlled transistorized first end and is connected with the first voltage end electricity, and the second end of described the first transistor, first is controlled transistorized the second end and is connected with output terminal electricity,
The first end of described transistor seconds is connected with second voltage end electricity, and the second end of described transistor seconds and second is controlled transistorized first end electricity and is connected, and described second controls transistorized the second end is connected with output terminal electricity;
The 3rd transistor between described adjacent fundamental oscillation unit, described the 3rd transistorized grid is connected with tertiary voltage end electricity, described the 3rd transistorized first end is connected with the output terminal electricity of one of them fundamental oscillation unit, the described the 3rd transistorized the second end is connected with the input end electricity of another fundamental oscillation unit, and described fundamental oscillation unit and the 3rd transistor series form ring oscillator.
2. the testing circuit of bias voltage temperature instability as claimed in claim 1, is characterized in that, the type of described the 3rd transistorized channel region is identical with the type of the channel region of transistor seconds.
3. the testing circuit of bias voltage temperature instability as claimed in claim 1, is characterized in that, utilizes described tertiary voltage end to make the 3rd transistorized channel region open.
4. the testing circuit of bias voltage temperature instability as claimed in claim 1, it is characterized in that, it is the PMOS transistor that described the first transistor, first is controlled transistor, it is nmos pass transistor that described transistor seconds, second is controlled transistor, the voltage of described the first voltage end is operating voltage, and the voltage of described second voltage end is no-voltage or negative bias.
5. the testing circuit of bias voltage temperature instability as claimed in claim 4, is characterized in that, the grid of described transistor seconds is metal gates.
6. the testing circuit of bias voltage temperature instability as claimed in claim 1, it is characterized in that, it is nmos pass transistor that described the first transistor, first is controlled transistor, it is the PMOS transistor that described transistor seconds, second is controlled transistor, the voltage of described second voltage end is operating voltage, and the voltage of described the first voltage end is no-voltage or negative bias.
7. the testing circuit of bias voltage temperature instability as claimed in claim 6, is characterized in that, the grid of described transistor seconds is metal gates or polysilicon gate.
8. the testing circuit of bias voltage temperature instability as described as claim 4 or 6, it is characterized in that, described PMOS transistor is enhancement mode PMOS transistor or depletion type PMOS transistor, and described nmos pass transistor is enhancement mode nmos pass transistor or depletion type nmos transistor.
9. the testing circuit of bias voltage temperature instability as claimed in claim 1, is characterized in that, utilizes described control voltage end to control first and control transistorized channel region and the transistorized channel region unlatching of the second control or close.
10. a detection method that adopts the testing circuit of bias voltage temperature instability as claimed in claim 1, is characterized in that, comprising:
Applying the first control voltage at described control voltage end makes the transistorized channel region of the first control open, second controls transistorized channel region closes, make the grid of transistor seconds be applied with bias voltage, transistor seconds is because the bias voltage temperature instability causes threshold voltage to be degenerated;
Apply the second control voltage at described control voltage end and make the transistorized channel region of the second control open, first controls transistorized channel region closes, described ring oscillator normal operation, and the detection frequency of detection ring oscillator;
According to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that the bias voltage temperature instability causes threshold voltage to be degenerated.
11. detection method as claimed in claim 10, is characterized in that, the detection frequency of described ring oscillator and the difference DELTA f=k between standard frequency
PΔ V
THP+ k
NΔ V
THN+ k
LΔ L, wherein said Δ V
THPFor the changing value of the transistorized threshold voltage of PMOS in the first transistor and transistor seconds, described Δ V
THNFor the changing value of the threshold voltage of nmos pass transistor in the first transistor and transistor seconds, the changing value that Δ L is the length of channel region in MOS transistor, described k
P, k
N, k
LFor constant.
12. detection method as claimed in claim 10, it is characterized in that, when described the first transistor, the first control transistor is the PMOS transistor, described transistor seconds, the second control transistor is nmos pass transistor, the voltage of described the first voltage end is operating voltage, the voltage of described second voltage end is no-voltage or negative bias, described the first control voltage is no-voltage or negative voltage, when described the second control voltage is operating voltage, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal operating voltage, make the grid of the first transistor and transistor seconds be applied with operating voltage, make transistor seconds because the positive bias temperature instability causes threshold voltage to be degenerated, and according to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that the positive bias temperature instability causes threshold voltage to be degenerated.
13. detection method as claimed in claim 10, it is characterized in that, when described the first transistor, the first control transistor is nmos pass transistor, described transistor seconds, the second control transistor is the PMOS transistor, the voltage of described second voltage end is operating voltage, the voltage of described the first voltage end is no-voltage or negative bias, described the first control voltage is operating voltage, when described the second control voltage is no-voltage or negative voltage, when described control voltage end applies the first control voltage, the output terminal of fundamental oscillation unit and the voltage of input end equal zero voltage or negative bias, make the grid of the first transistor and transistor seconds be applied with no-voltage or negative bias, make transistor seconds because Negative Bias Temperature Instability causes threshold voltage to be degenerated, and according to the detection frequency of described ring oscillator and the difference between standard frequency, the judgement transistor seconds is because the degree that Negative Bias Temperature Instability causes threshold voltage to be degenerated.
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