CN102811055A - Biasing circuit of constant-amplitude voltage-controlled ring oscillator - Google Patents

Abstract

The invention discloses a biasing circuit of a constant-amplitude voltage-controlled ring oscillator. The biasing circuit comprises a biasing voltage VBN generating circuit and a biasing voltage VBP generating circuit. According to the scheme, an operational amplifier is used with the biasing circuit, a negative feedback principle of the operational amplifier is utilized, the tail current source of the ring oscillator and the voltage of a drain terminal of a load circuit are respectively clamped to two reference levels, the limitation that the amplitude of oscillating signals of the voltage-controlled ring oscillator is changed along with change of control voltage is removed, constancy of the amplitude of the signals is ensured to be kept under optional oscillating frequencies, and the purpose of reducing phase noises of the voltage-controlled ring oscillator is achieved. The biasing circuit of the constant-amplitude voltage-controlled ring oscillator can be widely applied to various high-speed clock signal circuits.

Description

The biasing circuit of uniform amplitude annular voltage controlled oscillator

Technical field

The present invention relates to a kind of biasing circuit of annular voltage controlled oscillator, particularly a kind of biasing circuit of annular voltage controlled oscillator of uniform amplitude, it is mainly used in the high-speed clock signal circuit.

Background technology

Voltage controlled oscillator is the essential elements in the phase-locked loop, and its performance has directly determined the performance of phase-locked loop.Ring oscillator is compared the LC oscillator, and itself and CMOS technology have the tuning range of better compatibility and broad, thereby are widely used in the various clock systems.

Phase noise is an important parameter of weighing oscillator, has directly determined the phase noise of phase-locked loop, thereby has influenced the performance of whole system.A lot of important literature are analyzed phase noise; Modeling; Hajimiri and Lee have proposed to utilize the shock-sensitive function, and (impulse sensitivity function ISF) analyzes oscillator phase, and oscillator is (referring to document: Hajimiri A and Lee T H at the phase noise of a certain frequency shift (FS) place; " A General Theory of Phase Noise in Electrical Oscillators " IEEE JSSC; Vo1.33, PP.179-194, Feb1998.):

Wherein, R _pWith C be output resistance, the electric capacity of each grade of ring oscillator, V _MaxBe the amplitude output signal of each grade of ring oscillator, ω ₀Be the oscillation center frequency, Δ ω is frequency shift (FS), and k is a Boltzmann constant, and T is an absolute temperature.From formula (1), can find out and increase V _MaxCan reduce the phase noise of oscillator, and the clock signal amplitude that at present a lot of annular voltage controlled oscillator produces changes along with the variation of control voltage, can not remain on and work under the constant amplitude situation, works as V _MaxCan cause the phase noise of circuit to become big when diminishing.

The delay unit circuit figure of annular voltage controlled oscillator commonly used is as shown in Figure 1; The circuit diagram of traditional endless voltage controlled oscillator biasing circuit is as shown in Figure 2, and Fig. 2 circuit provides bias voltage for Fig. 1 circuit, and this biasing circuit can be the bias voltage of delay cell with the control voltage transitions; Make change the time of delay of delay cell; Thereby the frequency of oscillation of oscillator changes with the control change in voltage, but under this combination of circuits, the clock signal amplitude of delay cell output is with the control change in voltage; Can not keep constant, the phase noise of ring oscillator changes.

Summary of the invention

For overcoming the inconstant problem of amplitude in the above-mentioned annular voltage controlled oscillator, the present invention proposes a kind of biasing circuit of ring oscillator of uniform amplitude, work to guarantee that ring oscillator remains under the uniform amplitude.

The biasing circuit of the ring oscillator of a kind of uniform amplitude of the present invention is characterized in that, it contains:

A bias voltage V _BNProduce circuit, comprise PMOS pipe M _P1, NMOS manages M _N1, operational amplifier OP ₁, resistance R ₁, wherein, M _P1Source electrode meet power supply V _DD, M _P1Grid meet bias voltage V _B, M _P1Drain electrode and M _N1Drain electrode, OP ₁Positive input terminal and R ₁An end link together, its tie point is A, R ₁Another termination control voltage V _Ctrl, OP ₁Negative input end connect reference voltage V _Ref1, OP ₁Output and M _N1Grid connect, its tie point is V _BN, M _N1Source ground; With

A bias voltage V _BPProduce circuit, comprise PMOS pipe M _P2, PMOS manages M _P3, NMOS manages M _N2, NMOS manages M _N3, operational amplifier OP ₂, resistance R ₂, wherein, M _P2, M _P3Source electrode meet power supply V jointly _DD, M _P2Grid link to each other and and M with source electrode _P3Drain electrode, M _N3Drain electrode, positive input terminal and the R of OP2 ₂An end link together, its tie point is B, M _P3Grid and OP ₂Output link to each other, its tie point is V _BP, OP ₂Negative input end and R ₂The other end link to each other and and reference voltage V _Ref2Be connected M _N3Grid meet power supply V _DD, M _N3Source electrode and M _N2Drain electrode be connected M _N2Grid meet bias voltage V _BN, M _N2Source ground.

Beneficial effect:

Circuit of the present invention with compare with traditional annular voltage controlled oscillator biasing circuit, have following characteristics:

The scheme of annular voltage controlled oscillator biasing circuit of the present invention through using operational amplifier and biasing circuit to combine; Utilize the negative-feedback principle of operational amplifier; On drain terminal voltage difference clamper to two reference level with ring oscillator tail current source, load circuit; Thereby realized the clamping circuit; The feasible oscillator signal amplitude of the annular voltage controlled oscillator of this structure that adopts keeps constant, and the oscillator signal amplitude of having removed annular voltage controlled oscillator is with controlling the restriction that change in voltage changes.Circuit of the present invention can the inhibit signal amplitude under any frequency of oscillation constant; As shown in Figure 4; Control voltage changes to 1.8V from 1.4V; And the clock signal amplitude of ring oscillator has only changed and has remained unchanged basically approximately, has avoided the phase noise of annular voltage controlled oscillator to change with control voltage.

Traditional annular voltage controlled oscillator biasing circuit; Its minimum signal amplitude is 1/2 of a maximum signal amplitudes; The phase noise 3dB that will rise at least, and can know that by formula (1) signal amplitude of circuit of the present invention can not cause the phase noise variation because of the variation of signal amplitude.

Description of drawings

Fig. 1 is the delay unit circuit figure of annular voltage controlled oscillator commonly used;

Fig. 2 is the circuit diagram of traditional annular voltage controlled oscillator biasing circuit;

Fig. 3 is the circuit diagram of annular voltage controlled oscillator biasing circuit of the present invention.

Fig. 4 is the simulation curve figure of annular voltage controlled oscillator biasing circuit of the present invention.

Embodiment

The circuit diagram of the annular voltage controlled oscillator biasing circuit of practical implementation of the present invention is as shown in Figure 3.It is mainly by a bias voltage V _BNProduce circuit and a bias voltage V _BPThe generation circuit is formed.Its concrete structure and annexation, interactively are identical with the summary of the invention part of this specification, no longer repeat here.

Embodiment of the present invention is not limited only to following description, combines accompanying drawing to further specify at present.

Operational amplifier OP ₁With NMOS pipe M _N1, PMOS manages M _P1, resistance R ₁Form closed loop, through the negative feedback characteristic of amplifier, with M _N1The drain terminal voltage control be reference voltage V _Ref1, produce the bias voltage V that offers ring oscillator simultaneously _BNOperational amplifier OP ₂With PMOS pipe M _P2, M _P3, NMOS manages M _N2, M _N3, resistance R ₂Form closed loop, through the negative feedback characteristic of amplifier, with M _P2, M _P3The drain terminal voltage control be reference voltage V _Ref2, produce the bias voltage V that offers ring oscillator simultaneously _BP

Operational amplifier OP ₁, resistance R ₁, NMOS manages M _N1, PMOS manages M _P1Constitute the close loop negative feedback loop, be used for controlling NMOS pipe M _N1Drain terminal voltage keep constant.

Operational amplifier OP ₁Be common differential operational amplifier, gain adopts the P pipe right as input difference greater than 40dB, guarantees that operational amplifier can be at lower common-mode voltage V _Ref1Near operate as normal.Bias voltage V _BBe used for controlling M _P1Electric current, be M _P1The overdrive voltage of about 200mV is provided, makes M _P1The bias current that produces can guarantee: in The whole control change in voltage scope, and M _N1Always work in the saturation region.

Amplifier OP ₂Be common differential operational amplifier, gain adopts the N pipe right as input difference greater than 40dB, guarantees that amplifier can be at higher common-mode voltage V _Ref2Near operate as normal.

Operational amplifier OP ₂, resistance R ₂, PMOS manages M _P2, M _P3, NMOS manages M _N2, M _N3, constitute the close loop negative feedback loop, be used for controlling PMOS pipe M _P2, M _P3Drain terminal voltage keep constant.

The simulation curve figure of annular voltage controlled oscillator biasing circuit of the present invention is as shown in Figure 4.Among Fig. 4, abscissa is that control voltage changes to the used time of 1.8V from 1.4V, and ordinate is the amplitude of oscillator signal, can be found out by the simulation result of Fig. 4, and along with the variation of control voltage, the signal amplitude of the oscillator of circuit of the present invention is constant.

Manufacturing process of the present invention is general Si-gate N trap 0.18 μ m CMOS technology.

The basic parameter of the PMOS in the circuit of the present invention, NMOS pipe, resistance is:

The threshold voltage V of NMOS pipe _T: 0.4V;

The threshold voltage V of PMOS pipe _T:-0.5V;

M _N1The breadth length ratio of grid: 110 μ m/2 μ m;

M _N2The breadth length ratio of grid: 55 μ m/2 μ m;

M _N3The breadth length ratio of grid: 2.4 μ m/0.18 μ m;

M _P1The breadth length ratio of grid: 60 μ m/0.18 μ m;

M _P2The breadth length ratio of grid: 16 μ m/0.18 μ m;

M _P3The breadth length ratio of grid: 8 μ m/0.18 μ m.

R ₁Resistance: 1k Ω.

R ₂Resistance: 2k Ω.

OP ₁Basic parameter: gain＞40dB, bandwidth＞1MHz.

OP ₂Basic parameter: gain＞40dB, bandwidth＞1MHz.

Claims (1)

1. the biasing circuit of a uniform amplitude annular voltage controlled oscillator is characterized in that, it contains:

A bias voltage V _BNProduce circuit, comprise PMOS pipe M _P1, NMOS manages M _N1, operational amplifier OP ₁, resistance R ₁, wherein, M _P1Source electrode meet power supply V _DD, M _P1Grid meet bias voltage V _B, M _P1Drain electrode and M _N1Drain electrode, OP ₁Positive input terminal and R ₁An end link together, its tie point is A, R ₁Another termination control voltage V _Ctrl, OP ₁Negative input end connect reference voltage V _Ref1, OP ₁Output and M _N1Grid connect, its tie point is V _BN, M _N1Source ground; With

A bias voltage V _BPProduce circuit, comprise PMOS pipe M _P2, PMOS manages M _P3, NMOS manages M _N2, NMOS manages M _N3, operational amplifier OP ₂, resistance R ₂, wherein, M _P2, M _P3Source electrode meet power supply V jointly _DD, M _P2Grid link to each other and and M with source electrode _P3Drain electrode, M _N3Drain electrode, positive input terminal and the R of OP2 ₂An end link together, its tie point is B, M _P3Grid and OP ₂Output link to each other, its tie point is V _BP, OP ₂Negative input end and R ₂The other end link to each other and and reference voltage V _Ref2Be connected M _N3Grid meet power supply V _DD, M _N3Source electrode and M _N2Drain electrode be connected M _N2Grid meet bias voltage V _BN, M _N2Source ground.

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