CN102760639A - Configurable process variation monitoring circuit and monitoring method for crystal particles - Google Patents
Configurable process variation monitoring circuit and monitoring method for crystal particles Download PDFInfo
- Publication number
- CN102760639A CN102760639A CN2011101077026A CN201110107702A CN102760639A CN 102760639 A CN102760639 A CN 102760639A CN 2011101077026 A CN2011101077026 A CN 2011101077026A CN 201110107702 A CN201110107702 A CN 201110107702A CN 102760639 A CN102760639 A CN 102760639A
- Authority
- CN
- China
- Prior art keywords
- path
- signal
- standard cell
- pattern
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a configurable process variation monitoring circuit and a monitoring method for crystal particles. The configurable process variation monitoring circuit comprises an annular oscillator, a frequency divider and a frequency detector, the annular oscillator comprises a plurality of first standard cells, a plurality of second standard cells and a plurality of multiplexers, an oscillation signal is generated in a first mode or a second mode according to a selective signal, the frequency divider is coupled with the annular oscillator, the frequency of the oscillation signal is divided by a frequency division multiple to generate a frequency division signal, the frequency detector is coupled with the frequency divider, and the period of the frequency division signal is counted by a base clock to generate an output counting value, wherein the output counting value is related to process variation of the crystal particles.
Description
Technical field
The present invention relates to a kind of supervisory circuit of process variation, particularly a kind of configurable supervisory circuit and method thereof at crystal grain stage process variation monitor.
Background technology
After the development of CMOS processing procedure got into nano-scale, the product yield became increasing because of the influence that process variation (processvariation) receives, and this has also increased the difficulty of yield lifting (yieldramp-up).Run into low yield (low yield) problem at present and can only depend on circuit design automatic tools supplier (Electronic Design Automation Vendor; EDA Vendor) the defect diagonsis instrument that is provided (defect diagnosis tool) is diagnosed defective locations (defectlocation).Generally diagnose, but the major function of this model is to seek the stationarity defective that causes because of the processing procedure instrument, can't simulate the influence that is caused by process variation with static error model (static fault model).
Existing a kind of mode of obtaining processing procedure information is by wafer factory feeler switch (test key) to be set in the cutting trench region of each wafer; Use and collect the processing procedure relevant information; Yet based on the consideration of area cost, the feeler switch of being put in every wafer is very limited, can't obtain comprehensive information; And after these feeler switchs can't remain into the cutting stage; Therefore still need follow approach in addition obtains more processing procedure information in the back, to promote follow-up diagnosis or debugger capacity, could effectively promote yield.
Also having a kind of mode is to build supervisory circuit (monitor) in chip (chip); But these supervisory circuits are for obtaining pinpoint accuracy; Be designed to analog circuit mostly, the framework of analog circuit is different with digital circuit, and because the design that customizes; Analog circuit can bear bigger process variation, can't know the influence that the reflection process variation causes digital circuit.
After wafer goes back to factory; Usually can do analysis to understand present processing procedure situation to yield, a kind of common analysis way is to use wafer map (wafer map) to understand the processing procedure situation, and this way needs each feeler switch is done measurement; Yet what when CP/FT volume production test environment, use is the tester table that involves great expense; Testing time must be compressed in order to avoid waste testing cost, and the testing time of this way is long, so testing cost is high.
Existing processing procedure information gathering mode is because must lean on measuring instrument or tester table to measure signal parameter; Therefore the measuring instrument that not only needs high-order; And might board itself can import bigger error, in addition since the IC assembly along with the processing procedure progress is constantly dwindled, also constantly lifting of speed simultaneously; The delay (delay) that caused of metal line this moment (wire) is relative will become obviously; Therefore the variation of metal line can not be ignored the influence of circuit speed, but the variation that existing method can't be measured metal line, causes not good or the like the problem of diagnostic function.
Summary of the invention
One of the object of the invention is to propose a kind of configurable process variation supervisory circuit of crystal grain.
One of the object of the invention is to propose a kind of configurable process variation method for supervising of crystal grain.
According to the present invention; A kind of configurable process variation supervisory circuit of crystal grain; Comprise a ring oscillator; This ring oscillator comprises a plurality of first standard cell elements, a plurality of second standard cell elements and a plurality of multiplexer, selects signal with one first pattern or one second mode producing, one oscillator signal according to one; One frequency divider couples this ring oscillator, with this oscillator signal of frequency division multiple frequency division, produces a fractional frequency signal; And one frequency detector couple this frequency divider, by the cycle of this fractional frequency signal of fundamental clock counting, produce an output count value; Wherein, this output count value is relevant with the process variation of this crystal grain.
According to the present invention, a kind of configurable process variation method for supervising of crystal grain comprises the following steps: to select signal that one ring oscillator is switched with one first pattern or one second mode producing, one oscillator signal according to one; With this oscillator signal of frequency division multiple frequency division, produce a fractional frequency signal; And, produce an output count value by the cycle that a fundamental clock is counted this fractional frequency signal; Wherein, this ring oscillator comprises a plurality of first standard cell elements, a plurality of second standard cell elements and a plurality of multiplexer, and it is relevant with the process variation of this crystal grain to export count value.
Description of drawings
Fig. 1 is the calcspar according to process variation supervisory circuit first embodiment of the present invention;
Fig. 2 is the circuit diagram according to ring oscillator one embodiment of the present invention;
Fig. 3 is the calcspar according to process variation supervisory circuit second embodiment of the present invention;
Fig. 4 is the circuit diagram according to another embodiment of ring oscillator of the present invention;
Fig. 5 is the flow chart according to process variation method for supervising one embodiment of the present invention; And
Fig. 6 is the flow chart according to another embodiment of process variation method for supervising of the present invention.
The primary clustering symbol description
100 process variation supervisory circuit 100a process variation supervisory circuits
102 ring oscillator 102a ring oscillators
1024 multiplexer 1024a multiplexers
1025 multiplexers, 1026 multiplexers
1027 multiplexers 1028 or door
104 frequency dividers, 106 frequency detectors
108 comparison circuits, 110 initialization circuits
Embodiment
The present invention proposes a kind of intragranular configurable process variation supervisory circuit and method for supervising thereof of being arranged at; With full-digital circuit design supervisory circuit; Completely present process variation that digital circuit bears so that carry out follow-up diagnosis, and by configurable setting, the time demand when further cooperating the volume production test; Rapid screening is fallen bad or is received the bigger crystal grain of processing procedure negative effect (die), keeps high identification capability simultaneously.
Fig. 1 is the calcspar according to first embodiment of the invention; Ring oscillator 102 comprises many oscillation paths that are made up of various criterion cell element (standard cell) series connection; According to path select signal ro_sel, configurablely produce oscillator signal S via different oscillation paths
F, frequency divider 104 according to input instruction prog_code to oscillator signal S
FCarry out frequency division, with the oscillator signal S of high frequency
FChange into the fractional frequency signal S of low frequency
D, frequency detector 106 detects fractional frequency signal S by frequency signal dss_clk again
DCycle, produce count value count_out.Process variation supervisory circuit 100 can be arranged in the crystal grain Anywhere, preferably, is arranged at crucial (power critical) zone of sequential key (timing critical) or power supply.
With reference to the circuit diagram of ring oscillator one embodiment of Fig. 2, it is made up of many groups of annular oscillation paths, and this sentences four groups is example.And each group oscillation path is all by forming with a kind of standard cell element, and is designed to configurable framework, so that independent circulation pattern and mixing circulation pattern to be provided.These standard cell elements are meant the standard logical unit that wafer factory is provided; For example NAND gate (NAND gate) and NOR gate (NOR gate) etc.; In the present embodiment; The first path RO1 is composed in series by a plurality of reverser NAND2 that NAND gate constitutes, and via multiplexer 1024 be coupled in select control circuit 1022 with or door (OR gate) between 1028, Third Road footpath RO3 is also same; The second path RO2 is composed in series by a plurality of reverser NOR2 that NOR gate constitutes, via multiplexer 1025 be coupled in select control circuit 1022 and or door 1028 between, the 4th path RO4 also with; Select control circuit 1022 according to selecting signal ro_sel; Under different mode, produce path enable signal ro_en0～ro_en3 and multiplex's enable signal wsort_en; For example under single cell element pattern (single-cell type mode), enable the first path RO1, the second path RO2, Third Road footpath RO3 or the 4th path RO4; With the running clock ro_clock that passes through or door 1028 outputs produce with different paths, oscillator signal S promptly shown in Figure 1
F, produce four count values that correspond to each path by frequency detector 106 again; Mix under the cell element pattern (mixed-cell type mode) one; Then enable the first path RO1, the second path RO2, Third Road footpath RO3 and the 4th path RO4 by path enable signal ro_en0～ro_en3; And switch multiplexer 1024～1027 changing oscillation path by multiplex's enable signal wsort_en, via the first path RO1～the 4th path RO4 or the output output one of door 1028 mix the running clock ro_clock of multiple cell element characteristic.Among other embodiment, or door 1028 can be realized by multiplexer.
The oscillator signal S that under different mode, produces
FAnd count value can be done utilization by different way; The process variation characteristic that count value comprised that produces under the for example single cell element pattern is more simple; The count value that produces through the first path RO1 only should be relevant with the process variation of NAND gate; The data of the NAND gate that therefore can be provided according to standard cell element storehouse (standard cell library), the delay that for example each NAND gate caused is after frequency divider 104 done suitable frequency division multiplying power and set; The count value that frequency detector 106 produces is compared with expected results; And judge degree that count value shows whether in permissible scope, the variation relevant information that therefore can provide different cell elements under same processing procedure, to take place can provide detailed information in the debug (debug) or (diagnosis) stage of diagnosis; With the diagnostic phases is example; Usually having the well-to-do time does measurement, and what need is the information that identification capability is arranged, and comes from the flaw in processing procedure, circuit design or the design process with the problem of judging low yield; Therefore when diagnostic phases, can process variation supervisory circuit shown in Figure 1 be switched to single cell element pattern, so that distinguish whether cell element of generation relevant (cell-dependent) or element relevant (device-dependent) variation are arranged.
Present embodiment also is designed to adopt the identical standard cell element with the first path RO1 and Third Road footpath RO3, and therefore the first path RO1 and the Third Road footpath count value that RO3 produced can be collected the information relevant with the processing procedure stability in view of the above in order to mutual comparison.The characteristic that the count value that produces under the mixing cell element pattern has been mixed the multiple standards cell element; Therefore detailed process variation information can't be provided; But this pattern can produce the oscillator signal that comprises various criterion cell element characteristic rapidly, thereby is adapted under the situation of free pressure, for example the volume production test phase; Judge the quality of crystal grain rapidly, as a standard of screening crystal grain.
In other embodiments, single cell element pattern can different order circulate, and for example earlier with first path RO1 output running clock ro_clock, then exports running clock with Third Road footpath RO3, then gets back to second path RO2 or the like; Mixing the cell element pattern also can have various variations, for example only via the first path RO1 and second path RO2 output running clock ro_clock.
Performance datas such as the due sequential of these standard cell elements (timing), power (power), delay (delay) and noise can be learnt by the standard cell element storehouse that wafer factory provides; Therefore; Input instruction prog_code promptly decides according to selected path and normative reference cell element storehouse, make frequency divider 104 with different frequency division multiplying powers to oscillator signal S
FCarry out frequency division, clock signal dss_clk is able to correctly to fractional frequency signal S
DCycle count, obtain good resolution (resolution).
Fig. 3 is the calcspar according to another embodiment of process variation supervisory circuit of the present invention; In process variation supervisory circuit 100a; Ring oscillator 102a has many oscillation paths, can do selection and switch oscillator signal S by path select signal ro_sel and cloth line options signal wire_sel
FThe generation path, frequency divider 104 is with oscillator signal S
FFrequency division is signal S
DAfter, producing output count value count_out by frequency detector 106, comparison circuit 108 will be exported count value count_out and compare with standard meter numerical value golden_value, produce screening signal wsort_go according to this.Because in the use of CP/FT volume production test environment is the tester table that involves great expense; Testing time must be compressed to reduce testing cost as far as possible; Therefore, when the CP/FT volume production is tested, can select for use mixing cell element pattern to measure number of times, the output count value count_out of measurement generation and the standard meter numerical value golden_value of expectation are compared to reduce; Directly signal wsort_go is screened in output; With current tested IC classification, for example when output count value count_out overgauge count value golden_value, just eliminate tested crystal grain.Standard meter numerical value golden_value can be through initialization circuit 110 decisions; Initialization circuit 110 can comprise user's interface; Supply the user to set up standard meter numerical value golden_value on their own; Can also just accomplish a look-up table earlier and be stored in the initialization circuit 110 in layout simulation's (Post-layout simulation) stage of IC design; Initialization circuit 110 can be according to current selected pattern and path, and this look-up table is selected corresponding standard meter numerical value golden_value certainly, to offer comparison circuit 108.In other embodiments, can also design many group standard meter numerical value, so that tested crystal grain is done classification more accurately.
Fig. 4 is the inner bay composition of ring oscillator 102a, compares with ring oscillator 102 shown in Figure 2, and the first path ROL1 among the ring oscillator 102a has comprised a plurality of reverser NAND2, long routing path W that are made up of NAND gate
L, normal routing path W
NAnd three multiplexer 1024a; The second path ROL2, Third Road footpath ROL3 and the 4th path ROL4 have also comprised long routing path, short routing path and corresponding multiplexer thereof respectively; For avoiding accompanying drawing too mixed and disorderly, therefore only the first path ROL1 is added label.The ring oscillator 102a that present embodiment proposes has eight kinds of oscillation paths; Therefore; Setting according to path select signal ro_sel and cloth line options signal wire_sel; Select control circuit 1022 to enable different paths, and cooperate multiplex (MUX) enable signal wsort_en and cloth line options signal wire_sel, under single cell element pattern and mixing cell element pattern by path enable signal ro_en0～ro_en3; Further select with long cloth ray mode or normal cloth ray mode output running clock ro_clock; For example when path enable signal ro_en0=1 ' b1 and multiplex's enable signal wsort_en=1 ' b0, during cloth line options signal wire_sel=1 ' b0, signal transmission meeting is via long wiring W
L, so the metal wire variation can have influence on cycle of oscillation, via the variation of observing cycle of oscillation, then the deducibility metal wire receives the size of processing procedure influence.When cloth line options signal wire_sel=1 ' b1, then signaling path is via normal wiring W
N, under this pattern, signal propagation delays (signalpropagation delay) mainly postpones (device delay) by element and determines.
When multiplex's enable signal wsort_en=1 ' b1; Signaling path can be walked around four oscillation paths; To mix cell element mode producing running clock ro_clock; Therefore the delay distortion that different cell element caused all can have influence on final result, therefore is able to judge whether the speed of crystal grain to be measured reaches standard rapidly.
Fig. 5 is the flow chart of process variation monitor mode one embodiment of proposition according to the present invention; Please with reference to Fig. 1, after step S501 began, ring oscillator 102 got into single cell element pattern at step S502; Select an oscillation path, produce oscillator signal S via this oscillation path at step S503
F, then in step S504, frequency divider 104 produces fractional frequency signal S with this oscillation signal frequency dividing
D, frequency detector 106 detects fractional frequency signal S in step S505
DCycle, obtain the output count value count_out of current oscillation path, get into step S507 again and select next oscillation path, get back to step S503; Output count value count_out supplies back-end circuit to collect, so that diagnose or debug in step S506 output.
Fig. 6 is the flow chart of another embodiment of process variation monitor mode of proposition according to the present invention; With reference to Fig. 3 it is described; After step S601 began, ring oscillator 102a got at step S602 and mixes the cell element pattern, and produces oscillator signal S in step S603 via mixed path
F, when step S604, frequency divider 104 divided oscillator signal S
FAnd generation fractional frequency signal S
D, frequency detector 106 again in step S605 according to fractional frequency signal S
DProduce the output count value of mixing cell element; Then get into step 606, comparison circuit 108 will be exported count value count_out and compare with standard value golden_value, produce judged result according to this; For example whether decision eliminates current tested crystal grain, gets into and finishes s607.
The process variation supervisory circuit that the present invention proposes can be arranged on the zones of different in the crystal grain, to obtain the process variation information of intragranular (intra-die); Can also be arranged on the different crystal grain in the same wafer, obtain the process variation information of intercrystalline (inter-die), can also be in the same area setting of different wafers, to obtain the process variation information of (cross-wafer) between wafer.The variation that the position is set is expected with the information gathering arrangement of exporting count value, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the present invention's covering scope.
Claims (18)
1. the configurable process variation supervisory circuit of a crystal grain comprises:
One ring oscillator comprises a plurality of first standard cell elements, a plurality of second standard cell elements and a plurality of multiplexer, selects signal with one first pattern or one second mode producing, one oscillator signal according to one;
One frequency divider couples said ring oscillator, with the said oscillator signal of a frequency division multiple frequency division, produces a fractional frequency signal; And
One frequency detector couples said frequency divider, by the cycle that a fundamental clock is counted said fractional frequency signal, produces an output count value;
Wherein, said output count value is relevant with the process variation of said crystal grain.
2. supervisory circuit according to claim 1, wherein, said ring oscillator comprises:
One first path comprises a plurality of first multiplexers and a plurality of first reversers that are made up of said these first standard cell elements;
One second path comprises a plurality of second multiplexers and a plurality of second reversers that are made up of said these second standard cell elements;
One selects control circuit, couples said first path and said second path, enables said first path, said second path or said first path and said second path according to said selection signal; And
One the 3rd multiplexer is coupled between said first path, second path and the output.
3. supervisory circuit according to claim 2, wherein, said first path and said second path comprise a long routing path and a normal routing path respectively.
4. supervisory circuit according to claim 3 also comprises one the 4th multiplexer, controlled switching so that said oscillator signal via said long routing path or said normal routing path and produce.
5. supervisory circuit according to claim 2, wherein, said oscillator signal produces via said first path or said second path under said first pattern, and is next via said first path and the generation of said second path in said second pattern.
6. supervisory circuit according to claim 5; Wherein, Said frequency division multiple is relevant with said first standard cell element or the said second standard cell element under said first pattern, and is relevant with said first standard cell element and the said second standard cell element under said second pattern.
7. supervisory circuit according to claim 1, wherein, said ring oscillator, said frequency divider and said frequency detector are arranged on the said crystal grain.
8. supervisory circuit according to claim 1 also comprises:
One initialization circuit provides a standard meter numerical value; And
One comparison circuit is compared said output count value with said standard meter numerical value, to produce a screening signal;
Wherein, said screening signal is in order to determine the classification of said crystal grain.
9. supervisory circuit according to claim 8, wherein, said initialization circuit comprises a user's interface and a buffer.
10. supervisory circuit according to claim 1, wherein, said these first standard cell elements are NAND gate, said these second standard cell elements are NOR gate.
11. the configurable process variation method for supervising of a crystal grain comprises the following steps:
Select signal that one ring oscillator is switched with one first pattern or one second mode producing, one oscillator signal according to one;
With the said oscillator signal of a frequency division multiple frequency division, produce a fractional frequency signal; And
By the cycle that a fundamental clock is counted said fractional frequency signal, produce an output count value;
Wherein, said ring oscillator comprises a plurality of first standard cell elements, a plurality of second standard cell elements and a plurality of multiplexer, and said output count value is relevant with the process variation of said crystal grain.
12. method for supervising according to claim 11, wherein, said ring oscillator comprises:
First path of forming by a plurality of first multiplexers and said these first standard cell elements;
Second path of forming by a plurality of second multiplexers and said these second standard cell elements;
One selects control circuit, couples said first path and said second path, enables said first path, said second path or said first path and said second path according to said selection signal; And
One the 3rd multiplexer is coupled between said first path, second path and the output.
13. method for supervising according to claim 12, wherein, said first path and said second path also comprise a long routing path and a normal routing path respectively.
14. method for supervising according to claim 13 also comprises one the 4th multiplexer, controlled switching so that said oscillator signal produce via said long routing path or said normal routing path.
15. method for supervising according to claim 12 wherein, saidly selects signal that the step that one ring oscillator switches with one first pattern or one second mode producing, one oscillator signal is comprised according to one:
Under said first pattern, produce said oscillator signal via said first path or said second path; And
Under said second pattern, produce said oscillator signal via said first path and said second path.
16. method for supervising according to claim 15, wherein, said with the said oscillator signal of a frequency division multiple frequency division, the step that produces a fractional frequency signal also comprises:
Under said first pattern, determine said frequency division multiple according to said first standard cell element or the delayed data of the said second standard cell element in a standard cell element storehouse; Or
Under said second pattern, determine said frequency division multiple according to said first standard cell element and the delayed data of the said second standard cell element in said standard cell element storehouse.
17. method for supervising according to claim 11 also comprises:
One standard meter numerical value is provided;
Said output count value is compared with said standard meter numerical value, to produce a screening signal; And
Classification according to the said crystal grain of said screening signal deciding.
18. method for supervising according to claim 11, wherein, said these first standard cell elements are NAND gate, and said these second standard cell elements are NOR gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101077026A CN102760639A (en) | 2011-04-27 | 2011-04-27 | Configurable process variation monitoring circuit and monitoring method for crystal particles |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101077026A CN102760639A (en) | 2011-04-27 | 2011-04-27 | Configurable process variation monitoring circuit and monitoring method for crystal particles |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102760639A true CN102760639A (en) | 2012-10-31 |
Family
ID=47055047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101077026A Pending CN102760639A (en) | 2011-04-27 | 2011-04-27 | Configurable process variation monitoring circuit and monitoring method for crystal particles |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102760639A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10402523B2 (en) | 2015-08-04 | 2019-09-03 | Industrial Technology Research Institute | System for monitoring electronic circuit and method for monitoring electronic circuit |
| CN112486224A (en) * | 2020-12-10 | 2021-03-12 | 安徽环瑞电热器材有限公司 | Bathroom equipment temperature control system and temperature control method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040049711A1 (en) * | 2002-09-06 | 2004-03-11 | Korson Steven P. | Oscillation based access time measurement |
| US20050195042A1 (en) * | 2004-03-04 | 2005-09-08 | International Business Machines Corporation | Method and ring oscillator circuit for measuring circuit delays over a wide operating range |
| CN1763553A (en) * | 2004-10-20 | 2006-04-26 | 国际商业机器公司 | Method and apparatus for rapid inline measurement of parameter spreads and defects in integrated circuit chips |
| US20070013452A1 (en) * | 2005-07-12 | 2007-01-18 | International Business Machines Corporation | Methods and apparatus for measuring change in performance of ring oscillator circuit |
| CN101192825A (en) * | 2006-12-01 | 2008-06-04 | 松下电器产业株式会社 | Semiconductor apparatus |
| TW200827748A (en) * | 2006-12-19 | 2008-07-01 | Nat Univ Tsing Hua | Apparatus for built-in speed grading and method for generating desired frequency for the same |
| US7417918B1 (en) * | 2004-09-29 | 2008-08-26 | Xilinx, Inc. | Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit |
| CN101373203A (en) * | 2007-08-21 | 2009-02-25 | 中芯国际集成电路制造(上海)有限公司 | Speed testing structure of ring-shaped oscillator |
| US20090167317A1 (en) * | 2004-12-15 | 2009-07-02 | Texas Instruments Incorporated | Apparatus And Method For Test, Characterization, And Calibration Of Microprocessor-Based And Digital Signal Processor-Based Integrated Circuit Digital Delay Lines |
| CN101490566A (en) * | 2006-07-20 | 2009-07-22 | 爱迪半导体株式会社 | Method and apparatus for detecting capacitance using a plurality of time division frequencies |
| US20100102890A1 (en) * | 2008-10-27 | 2010-04-29 | Asic North, Inc. | Variable-Loop-Path Ring Oscillator Test Circuit and Systems and Methods Utilizing Same |
| US7831873B1 (en) * | 2007-03-07 | 2010-11-09 | Xilinx, Inc. | Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits |
-
2011
- 2011-04-27 CN CN2011101077026A patent/CN102760639A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040049711A1 (en) * | 2002-09-06 | 2004-03-11 | Korson Steven P. | Oscillation based access time measurement |
| US20050195042A1 (en) * | 2004-03-04 | 2005-09-08 | International Business Machines Corporation | Method and ring oscillator circuit for measuring circuit delays over a wide operating range |
| US7417918B1 (en) * | 2004-09-29 | 2008-08-26 | Xilinx, Inc. | Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit |
| CN1763553A (en) * | 2004-10-20 | 2006-04-26 | 国际商业机器公司 | Method and apparatus for rapid inline measurement of parameter spreads and defects in integrated circuit chips |
| US20090167317A1 (en) * | 2004-12-15 | 2009-07-02 | Texas Instruments Incorporated | Apparatus And Method For Test, Characterization, And Calibration Of Microprocessor-Based And Digital Signal Processor-Based Integrated Circuit Digital Delay Lines |
| US20070013452A1 (en) * | 2005-07-12 | 2007-01-18 | International Business Machines Corporation | Methods and apparatus for measuring change in performance of ring oscillator circuit |
| US7190233B2 (en) * | 2005-07-12 | 2007-03-13 | International Business Machines Corporation | Methods and apparatus for measuring change in performance of ring oscillator circuit |
| CN101490566A (en) * | 2006-07-20 | 2009-07-22 | 爱迪半导体株式会社 | Method and apparatus for detecting capacitance using a plurality of time division frequencies |
| CN101192825A (en) * | 2006-12-01 | 2008-06-04 | 松下电器产业株式会社 | Semiconductor apparatus |
| TW200827748A (en) * | 2006-12-19 | 2008-07-01 | Nat Univ Tsing Hua | Apparatus for built-in speed grading and method for generating desired frequency for the same |
| US7831873B1 (en) * | 2007-03-07 | 2010-11-09 | Xilinx, Inc. | Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits |
| CN101373203A (en) * | 2007-08-21 | 2009-02-25 | 中芯国际集成电路制造(上海)有限公司 | Speed testing structure of ring-shaped oscillator |
| US20100102890A1 (en) * | 2008-10-27 | 2010-04-29 | Asic North, Inc. | Variable-Loop-Path Ring Oscillator Test Circuit and Systems and Methods Utilizing Same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10402523B2 (en) | 2015-08-04 | 2019-09-03 | Industrial Technology Research Institute | System for monitoring electronic circuit and method for monitoring electronic circuit |
| CN112486224A (en) * | 2020-12-10 | 2021-03-12 | 安徽环瑞电热器材有限公司 | Bathroom equipment temperature control system and temperature control method thereof |
| CN112486224B (en) * | 2020-12-10 | 2022-03-18 | 安徽环瑞电热器材有限公司 | Bathroom equipment temperature control system and temperature control method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9128153B2 (en) | Micro-granular delay testing of configurable ICs | |
| US20140101500A1 (en) | Circuits and methods for functional testing of integrated circuit chips | |
| US7810000B2 (en) | Circuit timing monitor having a selectable-path ring oscillator | |
| CN102520332A (en) | Wafer testing device and method for the same | |
| CN114397561B (en) | Timing error detection circuit, method and electronic equipment | |
| TWI427307B (en) | Configurable process variation monitor circuit of die and monitor method thereof | |
| US7620862B1 (en) | Method of and system for testing an integrated circuit | |
| US8127191B2 (en) | Control method for semiconductor integrated circuit and semiconductor integrated circuit | |
| US7644385B1 (en) | Programmable logic device with performance variation compensation | |
| CN102760639A (en) | Configurable process variation monitoring circuit and monitoring method for crystal particles | |
| CN101165502B (en) | Tester simultaneous test method | |
| CN103200040A (en) | Interface signal quality testing method and system based on special chip | |
| US10107859B1 (en) | Determining test conditions for at-speed transition delay fault tests on semiconductor devices | |
| US8441277B2 (en) | Semiconductor testing device, semiconductor device, and testing method | |
| JP2004246557A (en) | Verification method and layout method for semiconductor integrated circuit | |
| US20070113136A1 (en) | Detection rate calculation method of test pattern, recording medium, and detection rate calculation apparatus of test pattern | |
| US7039842B1 (en) | Measuring propagation delays of programmable logic devices | |
| TWI684774B (en) | Circuit applied for multi-scan mode testing | |
| US20210295939A1 (en) | A digital circuit testing and analysis module, system and method thereof | |
| Jahanirad et al. | BIST-based online test approach for SRAM-based FPGAs | |
| Pradeep et al. | An optimised SDD ATPG and SDQL computation method across different pattern sets | |
| US20060001434A1 (en) | Method of inspecting actual speed of semiconductor integrated circuit | |
| TWI416147B (en) | Method for creating test clock domain during integrated circuit design and associated computer readable medium | |
| Kampmann et al. | Design for small delay test-a simulation study | |
| US20170010320A1 (en) | Reducing test time and system-on-chip (soc) area reduction using simultaneous clock capture based on voltage sensor input |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121031 |