CN102736006A - Test structure and test method for negative bias temperature instability of semiconductor device - Google Patents

Test structure and test method for negative bias temperature instability of semiconductor device Download PDF

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CN102736006A
CN102736006A CN2011100841978A CN201110084197A CN102736006A CN 102736006 A CN102736006 A CN 102736006A CN 2011100841978 A CN2011100841978 A CN 2011100841978A CN 201110084197 A CN201110084197 A CN 201110084197A CN 102736006 A CN102736006 A CN 102736006A
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voltage
negative bias
test
grid
bias
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CN102736006B (en
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冯军宏
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Abstract

The invention discloses a test structure for negative bias temperature instability (NBTI) of a semiconductor device. The test structure includes a bias voltage output device. When grid voltages of a semiconductor device are turned from stress negative bias voltages to test voltages or from test voltages to stress negative bias voltages, the bias voltage output device outputs maintaining voltages that are less than zero to grid electrodes; therefore, during the whole NBTI test process, all grid electrodes can be connected to negative bias voltages, so that an occurrence of a recovery effect can be avoided and thus accuracy of an NBTI test result can be improved. Meanwhile, the invention also discloses a test method for negative bias temperature instability of semiconductor device. According to the method, when voltages of grid electrodes are turned from stress negative bias voltages to test voltages or from test voltages to stress negative bias voltages, maintaining voltages that are less than zero are outputted to the grid electrodes; therefore, during the whole NBTI test process, all grid electrodes can be connected to negative bias voltages, so that an occurrence of a recovery effect can be avoided and thus accuracy of an NBTI test result can be improved.

Description

The test structure of semiconductor devices negative bias thermal instability and method of testing
Technical field
The present invention relates to the semiconductor test technical field, relate in particular to a kind of test structure and method of testing of semiconductor devices negative bias thermal instability.
Background technology
Along with dwindling of microelectronic component physical dimension, properties of integrated circuit is responsive more to microscopic defect, and more and more near its basic reliability limit, integrity problem is more and more outstanding for various technologies.Wherein, negative bias thermal instability (NBTI, Negative Bias TemperatureInstability) is the key factor that influences the MOS device reliability.The PMOS degeneration that is caused by the NBTI effect becomes the principal element that influences device lifetime gradually, and it degenerates even more serious than the NMOS life-span of being caused by hot carrier's effect.
The NBTI effect is that (usually>100 ℃) applies certain minus gate voltage biasing to the PMOS grid and cause because at high temperature, and this situation all possibly run in the device aging and the course of work.The influence that the NBTI effect causes shows as drain saturation current and mutual conductance constantly reduces, and threshold voltage shift constantly increases, and sub-threshold slope constantly reduces.The variation of these parameters may increase the signal delay in the sequential circuit, thereby causes timing drift.In Analogous Integrated Electronic Circuits; Particularly in the application of some parameter matching; The circuit working condition can apply asymmetrical bias stress to the transistor of coupling, thereby causes tangible parameter mismatch, and this will cause degenerating of device performance under reduction and the condition of work of yield rate in the ageing process.Mechanism prediction is arranged, and after the gate oxide thickness of MOS device was less than some, the NBTI effect will be above the influence of other various factors, and the main influence that become device lifetime is machine-processed.
Therefore, in order to assess product and check product exactly, generally all comprise the NBTI test in the present reliability testing.
Please refer to Fig. 1 to Fig. 2, wherein, Fig. 1 is traditional NBTI test structure synoptic diagram, and Fig. 2 is the added voltage synoptic diagram of device grids in the traditional NBTI test process.Like Fig. 1 and shown in Figure 2, traditional NBTI test at first adds stress negative bias Vstress at the grid g of MOS device, and at this moment, grid g scoops out power negative bias Vstress, tagma b ground connection GND, i.e. grid voltage Vg=Vstress, bulk voltage Vb=GND; Remove said stress negative bias Vstress then, and add test voltage and carry out the device electric parameter detecting, at this moment; Grid g and drain electrode d all meet test voltage Vmeasure, the equal ground connection GND of tagma b and source electrode s, i.e. Vg=Vd=Vstress; Vb=Vs=GND; Wherein, Vd is a drain voltage, and Vs is a source voltage; And after removing said stress negative bias before add test voltage Vmeasure; Bias voltage on the said grid g is zero; Be ground connection GND, usually this section period with above-mentioned grounded-grid GND is called stand-by period Twait, and this is by the ardware feature decision of tester table.
Yet; Because there is serious recovery (Recovery) effect in the NBTI effect; Be that the electrical parameter decline that the NBTI effect causes can recover 80% at most after removing current field condition, even in 1 second after current field condition removes, just can recover 50%; And above-mentioned traditional NBTI method of testing is removing the stress negative bias to this section process that adds test voltage; Grid g is ground connection GND, thereby causes traditional NB TI test to have serious recovery Effects, makes the follow-up device electric parameter detecting that carries out can not reflect the influence that the NBTI effect of device causes exactly.
In order to address this problem, the measure of taking at present has:
(1) through the adjustment tool parameters, shorten stand-by period Twait as far as possible, yet owing to stand-by period Twait is determined by board hardware, so shortening amount is limited;
(2) adopt instantaneous method of testing (On-the-fly method); In the method, the added voltage synoptic diagram of device grids is as shown in Figure 3, in the test process of NBTI; The voltage of device grids g is directly reduced to test voltage Vmeasure by stress negative bias Vstress; And, therefore, can avoid in the NBTI test process, producing recovery Effects without the process of ground connection GND.Yet said instantaneous method of testing is being carried out silicon chip level reliability (WLR; When WaferLevel Reliability) testing; Need special source measuring unit (SMU, Power SourceMeasure Unit), said source measuring unit can not use on traditional tester table; And for package level reliability (PLR, Package Level Reliability) test, because the restriction of concurrent testing, this instantaneous method of testing is difficult to be applied.
Therefore, be necessary existing NBTI test is improved.
Summary of the invention
The object of the present invention is to provide a kind of test structure and method of testing of semiconductor devices negative bias thermal instability, to improve the NBTI precision of test result.
For addressing the above problem; The present invention proposes a kind of test structure of semiconductor devices negative bias thermal instability; Wherein, said semiconductor devices comprises grid, source electrode, drain electrode and body electrode, and said grid links to each other with a bias voltage output unit; When adding stress negative bias or test voltage on the said grid, said bias voltage output unit does not influence the voltage on the said grid; Turn to during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage the stress negative bias during, said bias voltage output unit is kept voltage to said grid output one, and the said value of keeping voltage is less than zero.
Optional, said bias voltage output unit comprises first resistance, diode and second resistance of series connection successively; One termination, one first bias voltage of said first resistance, the said diode of its another termination; The said grid of a termination that said second resistance is connected with said diode, said stress negative bias of its another termination or test voltage; During the voltage of the said second resistance other end is by stress negative bias slew test voltage or by test voltage, turn to the stress negative bias during, said diode is opened, under other situation, said diode breaks off.
Optional, the said computing formula of keeping voltage is:
V H = R 2 R 1 + R 2 V 1
Wherein, V HFor keeping voltage, R 1Be the resistance of first resistance, R 2Be the resistance of second resistance, V 1It is first bias voltage.
Optional, R 2>R 1
Optional, R 2>5R 1
Optional; The absolute value of said first bias voltage is less than the absolute value of said test voltage; The absolute value of said test voltage is less than the absolute value of said stress negative bias, and when the absolute value of said grid voltage during less than the absolute value of said first bias voltage, said diode is opened.
Optional, when said grid scoops out the power negative bias, said body electrode grounding; When said grid connect test voltage, said drain electrode connect test voltage, and said source electrode and said body electrode grounding.
Simultaneously, for addressing the above problem, the present invention also proposes a kind of method of testing of semiconductor devices negative bias thermal instability, and this method utilizes the test structure of above-mentioned semiconductor devices negative bias thermal instability to test, and comprises the steps:
(1) grid with said semiconductor devices scoops out the power negative bias, and said grid is under the negative bias stress;
(2) remove said stress negative bias, add toward said grid and keep voltage;
(3) remove the said voltage of keeping, said grid is connect test voltage, said semiconductor devices is carried out electric performance test.
Compared with prior art; The test structure of semiconductor devices negative bias thermal instability provided by the invention, through increasing by a bias voltage output unit, said bias voltage output unit during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage, turn to the stress negative bias during; Keep voltage to said grid output one; And the said value of keeping voltage is less than zero, thereby makes that in the test process of whole NBTI, said grid all is connected to negative bias; Therefore can avoid the generation of recovery Effects, improve the NBTI precision of test result.
Compared with prior art; The method of testing of semiconductor devices negative bias thermal instability provided by the invention; Through turn to during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage the stress negative bias during, keep voltage to said grid output one, and the said value of keeping voltage is less than zero; Thereby make in the test process of whole NBTI; Said grid all is connected to negative bias, therefore can avoid the generation of recovery Effects, has improved the NBTI precision of test result.
Description of drawings
Fig. 1 is traditional NBTI test structure synoptic diagram;
Fig. 2 is the added voltage synoptic diagram of device grids in the traditional NBTI test process;
Fig. 3 carries out the added voltage synoptic diagram of device grids in the NBTI test process for the instantaneous method of testing of existing employing;
The NBTI test structure synoptic diagram that Fig. 4 provides for the embodiment of the invention;
The added voltage synoptic diagram of device grids in the NBTI method of testing that Fig. 5 provides for the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the test structure and the method for testing of the semiconductor devices negative bias thermal instability of the present invention's proposition are done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; A kind of test structure of semiconductor devices negative bias thermal instability is provided, and this structure comprises a bias voltage output unit, said bias voltage output unit turn to during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage the stress negative bias during; Keep voltage to said grid output one; And the said value of keeping voltage is less than zero, thereby makes that in the test process of whole NBTI, said grid all is connected to negative bias; Therefore can avoid the generation of recovery Effects, improve the NBTI precision of test result; Simultaneously; The present invention also provides a kind of method of testing of semiconductor devices negative bias thermal instability; This method through turn to during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage the stress negative bias during, keep voltage to said grid output one, and the said value of keeping voltage is less than zero; Thereby make in the test process of whole NBTI; Said grid all is connected to negative bias, therefore can avoid the generation of recovery Effects, has improved the NBTI precision of test result.
Please refer to Fig. 4 and Fig. 5, wherein, the added voltage synoptic diagram of device grids in the NBTI method of testing that the NBTI test structure synoptic diagram that Fig. 4 provides for the embodiment of the invention, Fig. 5 provide for the embodiment of the invention.In conjunction with Fig. 4 and Fig. 5; The test structure of the semiconductor devices negative bias thermal instability that the embodiment of the invention provides comprises a bias voltage output unit; Wherein, said semiconductor devices comprises grid g, source electrode s, drain electrode d and body electrode b, and said grid g links to each other with said bias voltage output unit; When adding stress negative bias or test voltage on the said grid g, said bias voltage output unit does not influence the voltage on the said grid g; Turn to during the voltage on the said grid g is by stress negative bias Vstress slew test voltage Vmeasure or by test voltage Vmeasure stress negative bias Vstress during; Said bias voltage output unit is kept voltage to said grid g output one, and the said value of keeping voltage is less than zero.
Further, said bias voltage output unit comprises first resistance R of series connection successively 1, diode D and second resistance R 2Said first resistance R 1A termination one first bias voltage V 1, the said diode D of its another termination; Said second resistance R 2The said grid g of a termination that connects with said diode D, its another termination said stress negative bias Vstress or test voltage Vmeasure; When said second resistance R 2The voltage of the other end by stress negative bias Vstress slew test voltage Vmeasure during or by test voltage Vmeasure turn to stress negative bias Vstress during, said diode D opens, under other situation, said diode D breaks off.
Further, the said computing formula of keeping voltage is:
V H = R 2 R 1 + R 2 V 1
Wherein, V HFor keeping voltage, R 1Be the resistance of first resistance, R 2Be the resistance of second resistance, V 1It is first bias voltage.
Further, R 2>R 1, preferably, R 2>5R 1Thereby, can guarantee the said first bias voltage V 1Can be added in said second resistance R to greatest extent 2On, make the said voltage V that keeps HAs far as possible near the said first bias voltage V 1
Further, the said first bias voltage V 1Absolute value less than the absolute value of said test voltage Vmeasure, the absolute value of said test voltage Vmeasure is less than the absolute value of said stress negative bias Vstress, when the absolute value of said grid voltage less than the said first bias voltage V 1Absolute value the time, said diode D opens.
Further, when said grid g scoops out power negative bias Vstress, said body electrode b ground connection; When said grid met test voltage Vmeasure, said drain electrode d met test voltage Vmeasure, and said source electrode s and said body electrode b ground connection; Thereby can measure the unit for electrical property parameters of semiconductor devices.
The principle of the test structure of the semiconductor devices negative bias thermal instability that the embodiment of the invention provides is following:
When said second resistance R 2Scoop out power negative bias Vstress, or during test voltage Vmeasure, said diode D closes, therefore, the electric current of semiconductor devices is very little, is about 10 -9A can ignore, therefore said second resistance R 2On voltage drop also can ignore, thereby make the voltage and the gate source voltage V of grid GsEquate, equal stress negative bias Vstress or test voltage Vmeasure, said bias voltage output unit does not exert an influence to the voltage stress biasing and the test of device;
As said gate source voltage V GsDuring=GND, the absolute value that meets grid voltage is less than the said first bias voltage V 1The condition of absolute value, therefore, said diode D opens, said bias voltage output unit is kept voltage V toward the grid input of device HThereby, make said second resistance R 2The voltage of the other end by stress negative bias Vstress slew test voltage Vmeasure during or by test voltage Vmeasure turn to stress negative bias Vstress during, therefore the bias voltage on the said grid is non-vanishing all the time, can not produce recovery Effects.
Simultaneously, the method for testing of the semiconductor devices negative bias thermal instability that the embodiment of the invention provides utilizes the test structure of above-mentioned semiconductor devices negative bias thermal instability to test, and comprises the steps:
(1) the grid g with said semiconductor devices scoops out power negative bias Vstress, and said grid g is under the negative bias stress;
(2) remove said stress negative bias Vstress, add toward said grid g and keep voltage V H
(3) remove the said voltage V that keeps H, said grid g is met test voltage Vmeasure, said semiconductor devices is carried out electric performance test.
In sum; The invention provides a kind of test structure of semiconductor devices negative bias thermal instability, this structure comprises a bias voltage output unit, said bias voltage output unit turn to during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage the stress negative bias during; Keep voltage to said grid output one; And the said value of keeping voltage is less than zero, thereby makes that in the test process of whole NBTI, said grid all is connected to negative bias; Therefore can avoid the generation of recovery Effects, improve the NBTI precision of test result; Simultaneously; The present invention also provides a kind of method of testing of semiconductor devices negative bias thermal instability; This method through turn to during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage the stress negative bias during, keep voltage to said grid output one, and the said value of keeping voltage is less than zero; Thereby make in the test process of whole NBTI; Said grid all is connected to negative bias, therefore can avoid the generation of recovery Effects, has improved the NBTI precision of test result.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (8)

1. the test structure of a semiconductor devices negative bias thermal instability; Wherein, Said semiconductor devices comprises grid, source electrode, drain electrode and body electrode, it is characterized in that, said grid links to each other with a bias voltage output unit; When adding stress negative bias or test voltage on the said grid, said bias voltage output unit does not influence the voltage on the said grid; Turn to during the voltage on the said grid is by stress negative bias slew test voltage or by test voltage the stress negative bias during, said bias voltage output unit is kept voltage to said grid output one, and the said value of keeping voltage is less than zero.
2. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 1 is characterized in that, said bias voltage output unit comprises first resistance, diode and second resistance of series connection successively; One termination, one first bias voltage of said first resistance, the said diode of its another termination; The said grid of a termination that said second resistance is connected with said diode, said stress negative bias of its another termination or test voltage; During the voltage of the said second resistance other end is by stress negative bias slew test voltage or by test voltage, turn to the stress negative bias during, said diode is opened, under other situation, said diode breaks off.
3. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 2 is characterized in that, the said computing formula of keeping voltage is:
V H = R 2 R 1 + R 2 V 1
Wherein, V HFor keeping voltage, R 1Be the resistance of first resistance, R 2Be the resistance of second resistance, V 1It is first bias voltage.
4. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 3 is characterized in that, R 2>R 1
5. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 4 is characterized in that, R 2>5R 1
6. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 5; It is characterized in that; The absolute value of said first bias voltage is less than the absolute value of said test voltage; The absolute value of said test voltage is less than the absolute value of said stress negative bias, and when the absolute value of said grid voltage during less than the absolute value of said first bias voltage, said diode is opened.
7. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 2 is characterized in that, when said grid scoops out the power negative bias, and said body electrode grounding; When said grid connect test voltage, said drain electrode connect test voltage, and said source electrode and said body electrode grounding.
8. the method for testing of a semiconductor devices negative bias thermal instability utilizes the test structure of each described semiconductor devices negative bias thermal instability of claim 1 to 7 to test, and it is characterized in that this method comprises the steps:
(1) grid with said semiconductor devices scoops out the power negative bias, and said grid is under the negative bias stress;
(2) remove said stress negative bias, add toward said grid and keep voltage;
(3) remove the said voltage of keeping, said grid is connect test voltage, said semiconductor devices is carried out electric performance test.
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CN103941172A (en) * 2013-01-22 2014-07-23 中芯国际集成电路制造(上海)有限公司 Semiconductor test apparatus and test method
US9404960B2 (en) 2013-09-30 2016-08-02 Globalfoundries Inc. On chip bias temperature instability characterization of a semiconductor device
CN108037438A (en) * 2017-12-13 2018-05-15 中国科学院新疆理化技术研究所 The test method that a kind of total dose irradiation influences PMOSFET Negative Bias Temperature Instabilities
CN111381140A (en) * 2018-12-29 2020-07-07 长鑫存储技术有限公司 Semiconductor element testing method and apparatus
CN111381139A (en) * 2018-12-29 2020-07-07 长鑫存储技术有限公司 Semiconductor device testing method and semiconductor device testing system
CN115061028A (en) * 2022-06-23 2022-09-16 四川锶未铼科技有限公司 Silicon carbide MOSFET threshold drift test circuit and test method

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CN101441245A (en) * 2007-11-19 2009-05-27 中芯国际集成电路制造(上海)有限公司 Method for testing temperature instability under minus bias pressure

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US20050278677A1 (en) * 2004-06-10 2005-12-15 Chartered Semiconductor Manufacturing Ltd. Novel test structure for automatic dynamic negative-bias temperature instability testing
CN101029910A (en) * 2007-03-22 2007-09-05 华为技术有限公司 Current inspecting circuit and device
CN101441245A (en) * 2007-11-19 2009-05-27 中芯国际集成电路制造(上海)有限公司 Method for testing temperature instability under minus bias pressure

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103941172A (en) * 2013-01-22 2014-07-23 中芯国际集成电路制造(上海)有限公司 Semiconductor test apparatus and test method
CN103941172B (en) * 2013-01-22 2016-12-28 中芯国际集成电路制造(上海)有限公司 Semiconductor test apparatus and method of testing
US9404960B2 (en) 2013-09-30 2016-08-02 Globalfoundries Inc. On chip bias temperature instability characterization of a semiconductor device
CN108037438A (en) * 2017-12-13 2018-05-15 中国科学院新疆理化技术研究所 The test method that a kind of total dose irradiation influences PMOSFET Negative Bias Temperature Instabilities
CN111381140A (en) * 2018-12-29 2020-07-07 长鑫存储技术有限公司 Semiconductor element testing method and apparatus
CN111381139A (en) * 2018-12-29 2020-07-07 长鑫存储技术有限公司 Semiconductor device testing method and semiconductor device testing system
CN111381140B (en) * 2018-12-29 2022-04-15 长鑫存储技术有限公司 Semiconductor element testing method and apparatus
CN111381139B (en) * 2018-12-29 2022-04-26 长鑫存储技术有限公司 Semiconductor device testing method and semiconductor device testing system
CN115061028A (en) * 2022-06-23 2022-09-16 四川锶未铼科技有限公司 Silicon carbide MOSFET threshold drift test circuit and test method

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