CN102508146A - Method for determining testing conditions for hot carrier injection stress - Google Patents
Method for determining testing conditions for hot carrier injection stress Download PDFInfo
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- CN102508146A CN102508146A CN2011103838854A CN201110383885A CN102508146A CN 102508146 A CN102508146 A CN 102508146A CN 2011103838854 A CN2011103838854 A CN 2011103838854A CN 201110383885 A CN201110383885 A CN 201110383885A CN 102508146 A CN102508146 A CN 102508146A
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Abstract
The invention provides a method for determining testing conditions for hot carrier injection stress. The method includes steps of selecting an MOS (metal dioxide semiconductor) device, and respectively measuring Isub-Vg curves under at least three different values Vd smaller than or equal to working voltage of the device; respectively obtaining the Isubmax corresponding to each Isub-Vg voltage curve, and reading voltage values Vg of the Isubmax; drawing a Vg-Vd relational graph by the aid of the values obtained from previous steps; fitting the Vg-Vd relational graph by the aid of a linear function, and obtaining a fitting formula; and calculating stress voltage values Vg under stress of the three values Vd according to the fitting formula obtained from the previous step, namely obtaining the testing conditions for HCI (hot carrier injection). The method can be used for testing HCI by the aid of a small amount of samples, and testing cost is reduced.
Description
Technical field
The present invention relates to the semiconducter device testing field, relate in particular to device hot carrier injection into test method, can effectively reduce specimen, reduce cost.
Background technology
As far as the VLSI (very large scale integrated circuits) manufacturing industry; Along with constantly reducing of MOSFET (mos field effect transistor) plant bulk; Semiconductor fabrication process has got into the deep-submicron epoch; And to the sub-micro development, at this moment, semiconductor device reliability more and more directly affects the performance and the serviceable life of the IC chip of making.But, because during MOS device size scaled down, the device WV does not have corresponding equal proportion and reduces, so, the inner electric field intensity of corresponding devices with device size reduce strengthen on the contrary.Therefore, in small size device, the lateral dimension of circuit is more and more littler; Cause channel length to reduce; Even less source-drain voltage also can form very high electric field intensity near drain terminal, because this transverse electric field effect, at the high electric area of drain terminal; Channel electrons obtains very big drift velocity and energy, becomes hot carrier.In deep submicron process, along with dwindling day by day of MOS device size, it is more and more serious that the hot carrier of MOS device is injected (HCI) effect, and the degeneration of the device performance that it causes is to influence one of key factor of MOS device reliability.Therefore, one of main test event of HCI test having become MOS device reliability test.
Because the injection of MOS device hot carrier is according to JEDEC (Joint Electron DeviceEngineering Council) standard; Therefore MOS device HCI test is also carried out according to the JEDEC standard; Being about to the MOS device is under the most serious situation of HCI; Load 3 different stress voltages (stressvoltage); Obtain degenerated curve, thereby, calculate the life-span of its hot carrier test under WV or 1.1 times of WVs according to life model according to the degeneration amplitude under 3 different stress voltages.No matter test or silicon wafer grade test for package level, according to the JEDEC standard, a kind of general HCI life test condition step is following: the first step, and selected 3 drain stress voltage Vd stress that are higher than WV test; In second step, under each drain stress voltage Vd stess, find the serious situation of HCI.Usually the serious situation of HCI is under the substrate current Isub maximum case; Therefore; Under each set drain stress voltage Vdstess; The MOS device is carried out substrate current and grid voltage Isub-Vg scanning, thereby find substrate current maximal value Isubmax, and the pairing Vg magnitude of voltage of Isubmax.Then; The HCI worst case of the pairing Vg magnitude of voltage of Isubmax and set drain stress voltage Vd stress having been formed this drain stress voltage Vd stress; Test condition just, and can make the degenerated curve under the drain stress voltage Vd stress; In the 3rd step,, calculate its life-span that hot carrier is tested under WV or 1.1 times of WVs according to life model according to the degeneration amplitude 3 drain stress voltage Vd stress under.According to the JEDEC standard, it is destructive under drain stress voltage Vd stress, carrying out the Isub-Vg curved scanning, and the MOS device after the scanning has received the HCI damage; Performance is degenerated, can not be used further to HCI stress test subsequently, therefore; For the HCI stress test; Not only need prepare the sample of stress test, need prepare to be used for confirming the sample of test condition simultaneously, increase testing cost.
In order to address the above problem; When carrying out the preparation of HCI test condition; Need seek redress to eliminate to come under the drain stress voltage Vd stress and carry out the destruction of Isub-Vg curved scanning the MOS device; But in the implementation process of reality, still there is sizable barrier, demands introducing the new method that effectively to improve above-mentioned defective urgently, increase the topmost problem of sample to solve the needs that face when the HCI method of testing is used in the semiconducter device testing field.
Summary of the invention
Technical matters to be solved by this invention provides the method that a kind of definite hot carrier is injected the stress test condition, needs in the general HCI method of testing to prepare to provide extra sample to be used for the HCI test condition to solve, thereby has further reduced testing cost.
For addressing the above problem, definite hot carrier that the present invention proposes is injected the method for stress test condition, and wherein the injection of MOS device hot carrier is based on the JEDEC standard, and this method comprises the steps:
Step 1: select a MOS device; Said device MOS is carried out the hot carrier injection experiments; Under different drain voltage Vd more than at least 3, measure the substrate current and the grid voltage Isub-Vg curve of said MOS device respectively, said drain voltage Vd is all smaller or equal to the WV of MOS device;
Step 2: for pairing substrate current of each drain voltage Vd and grid voltage Isub-Vg curve, find out substrate current maximal value Isubmax respectively, and read the pairing grid voltage Vg of substrate current maximal value Isubmax value;
Step 3: the pairing grid voltage Vg of substrate current maximal value Isubmax value under the different drain voltage Vd that obtain according to step 2, produce grid voltage and drain voltage Vg-Vd graph of a relation;
Step 4: grid voltage and drain voltage Vg-Vd graph of a relation that step 3 obtains are used linear function fit, obtain fitting formula,
y＝Ax+B
Wherein, x is drain voltage Vd value, and y represents the Vg magnitude of voltage of the MOS device of being tested that match draws, and A, B are constant;
Step 5: according to the fitting formula of step 4; Select for use at least 3 drain stress voltage Vd stress as the substitution of x value; The y value that calculates respectively as gate stress voltage Vg stress value, and is constituted HCI stress test condition respectively by each drain stress voltage Vd stress value and corresponding gate stress voltage Vg stress value thereof.
Compare with the HCI test MOS device method of traditional common; The present invention tests through 3 drain voltage Vd data that are lower than WV that original selected 3 drain stress voltage Vd stress test datas that are higher than WV are changed in the step 1; And scan pairing substrate current and grid voltage Isub-Vg curve under each drain voltage Vd that is lower than WV; Then, find substrate current maximal value Isubmax and the pairing grid voltage Vg of substrate current maximal value Isubmax value in each root substrate current and the grid voltage Isub-Vg curve through step 2, then; Find pairing grid voltage Vg value under the different drain voltage Vd through step 3; Thereby produce grid voltage and drain voltage Vg-Vd graph of a relation, then, can be through grid voltage and the drain voltage Vg-Vd graph of a relation in the step 3; Obtain fitting formula through linear function; At last, obtain HCI stress test condition so that the follow-up HCI of carrying out stress test, obtain the electricity degraded performance of said MOS device according to the fitting formula in the step 4.This shows; Because the voltage that substrate current in the step 1 and grid voltage Isub-Vg curved scanning are loaded does not all surpass WV; For MOS device not damaged, therefore, above-mentioned MOS device still can be used as tested device and is used for later HCI stress test.Because the formulation of HCI stress test condition is reckoning and obtains, so need not to prepare the extra sample that is used to formulate the stress test condition.Therefore, the present invention only need provide the sample under the HCI test condition can carry out the formulation and the test of HCI stress test condition, has reduced sample, has practiced thrift testing cost.Simultaneously; In semiconductor fabrication process; The method that described definite hot carrier is injected the stress test condition not only can obtain the life-span that hot carrier is injected through the method for encapsulation utmost point test, and, also can obtain the life-span that hot carrier is injected through silicon wafer grade test; Therefore, can the actual test of strain need.
Description of drawings
Fig. 1 injects the method flow of stress test condition for the present invention confirms hot carrier;
Fig. 2 is that test MOS device of the present invention is at substrate current under the different drain voltage Vd and the graph of a relation between the grid voltage Isub-Vg;
Fig. 3 is test MOS device of the present invention Vg-Vd graph of a relation for grid voltage under different drain voltages.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Referring to Fig. 1, the method flow that a kind of definite hot carrier provided by the present invention is injected the stress test condition is:
Step 1: select a MOS device; Said device MOS is carried out the hot carrier injection experiments; Under different drain voltage Vd more than at least 3, measure the substrate current and the grid voltage Isub-Vg curve of said MOS device respectively, said drain voltage Vd is all smaller or equal to the WV of MOS device;
Because the voltage that substrate current in the step 1 and grid voltage Isub-Vg curved scanning are loaded does not all surpass WV, for MOS device not damaged, therefore, above-mentioned MOS device still can be used for later HCI test.
Step 2: for pairing substrate current of each drain voltage Vd and grid voltage Isub-Vg curve, find out substrate current maximal value Isubmax respectively, and read the pairing grid voltage Vg of substrate current maximal value Isubmax value;
Step 3: the pairing grid voltage Vg of substrate current maximal value Isubmax value under the different drain voltage Vd that obtain according to step 2, produce grid voltage and drain voltage Vg-Vd graph of a relation;
Step 4: grid voltage and drain voltage Vg-Vd graph of a relation that step 3 obtains are used linear function fit, obtain fitting formula,
y＝Ax+B (1)
Wherein, x is drain voltage Vd value, and y represents the grid voltage Vg value of the MOS device of being tested that match draws, and A, B are constant;
Through said fitting formula,, just can calculate to obtain the y value as long as confirm the x value.
Step 5: according to the fitting formula of step 4; Select for use at least 3 drain stress voltage Vd stress as the substitution of x value; The y value that calculates respectively as gate stress voltage Vg stress value, and is constituted hot carrier injection stress HCI stress test condition respectively by each drain stress voltage Vd stress value and corresponding gate stress voltage Vg stress value thereof.
Through grid voltage in the step 3 and drain voltage Vg-Vd graph of a relation; Confirm the constant A of formula (1), B value with linear functional relation with carrying out match between grid voltage Vg and the drain voltage Vd; The fitting formula that draws was hot carrier and injected the derive computing formula of HCI stress test condition of can being used to of being tested behind the MOS device this moment; And constant A, B value can adopt data fitting software; For example software such as matlab carries out match, or can directly adopt numerical method to carry out artificial fitting's calculating.Be to adopt the artificial fitting to calculate in the embodiment of the invention.
The WV that one embodiment of the invention obtain for preparation under 0.5um technology with tested object is that the nmos device of 5V is an example; In conjunction with accompanying drawing 2 and accompanying drawing 3; The method that a kind of definite hot carrier is injected the stress test condition is described in detail, yet those skilled in the art should know how this method is applied to the PMOS device.Generally speaking, need to select at least 3 different drain voltages that the MOS device is carried out the hot carrier injection experiments, just list in one embodiment of the invention and lift 3 different drain voltages.
The hot carrier injection into test MOS device method is normally based on the JEDEC standard, and drain terminal and grid all load certain voltage, source end and substrate ground connection, test MOS device under certain stress condition.
Select a MOS device; Based on the JEDEC standard, said device MOS is carried out hot carrier inject, measure substrate current and the grid voltage Isub-Vg curve of said MOS device under drain voltage Vd=5V; Referring to Fig. 2; Horizontal ordinate is grid voltage Vg, and ordinate is substrate current Isub, obtains the pairing grid voltage Vg of the substrate current maximal value Isubmax value under the said drain voltage Vd=5V; Substrate current maximal value Isubmax in said substrate current and the grid voltage Isub-Vg curve is 3.9E-5A, and corresponding grid voltage Vg value is 2.1V.
Change drain voltage Vd value; Remeasure substrate current and the grid voltage Isub-Vg curve of said MOS device under the drain voltage Vd=4.5V after the change, the pairing grid voltage Vg of the substrate current maximal value Isubmax value that obtains under said drain voltage=4.5V is 1.95V (figure does not show).
Continue to change drain voltage Vd value again, obtain substrate current and grid voltage Isub-Vg curve under the different drain voltage Vd values respectively, same method obtains the pairing grid voltage Vg of substrate current maximal value Isubmax value.In the present embodiment, drain voltage Vd value is selected 5V, 4.5V, 4V, 3.5V and 3V respectively for use, and pairing grid voltage Vg is by shown in the table (1) under the different drain voltage Vd that obtain:
Table (1)
| Vd(V) | Vg(V) |
| 5 | 2.1 |
| 4.5 | 1.95 |
| 4 | 1.8 |
| 3.5 | 1.6 |
| 3 | 1.45 |
Said different drain voltage Vd is all smaller or equal to the WV of MOS device; And described each drain voltage value can be according to the real work voltage difference of the MOS device of choosing respectively by the certain intervals value; For example; Tested object is the MOS device of 5V in one embodiment of the invention, and drain voltage can be 5V, 4.5V, 4V, 3.5V and 3V according to the distribution value that is spaced apart 0.5V; Like tested object is the MOS device of 1V; Drain voltage can be according to the distribution value that is spaced apart 0.2V or 0.1V; When by the distribution value of 0.2V, be 1V, 0.8V, 0.6V and 0.4V, when by the distribution value of 0.1V, be 1V, 0.9V, 0.8V, 0.7V and 0.6V; When being other WVs, can test according to industry standard according to actual test case according to the JEDEC standard like tested object.
To show the mapping of (1) drain voltage Vd and grid voltage Vg relation, referring to Fig. 3, wherein horizontal ordinate is drain voltage Vd, and ordinate is grid voltage Vg., calculate through the artificial fitting carrying out match between grid voltage Vg and the drain voltage Vd with linear function, can confirm constant A=0.33, B=0.46 obtains fitting formula at last, and the fitting formula in this instance is y=0.33x+0.46.The fitting formula that draws was hot carrier and injected the derive computing formula of HCI stress test condition of can being used to of being tested behind the MOS device this moment.Wherein, said drain voltage Vd is not limited to parameter value cited in one embodiment of the invention, as long as drain voltage Vd is no more than the derivation that the WV of MOS device all can be used for fitting formula.
Then, select 3 drain stress voltage Vd stress for use, all be higher than normal working voltage, and as the drain voltage of follow-up HCI stress test.For the voltage of selecting the HCI stress test for use; Be generally and be no more than 70% of drain terminal voltage breakdown; In this scope, the relation of grid voltage Vg and drain stress voltage Vd stress still meets the rule of linear function, promptly above-mentioned fitting formula y=0.33x+0.46.The condition of the HCI stress test selected for use of 5V device is Vd=6V in the present embodiment, 6.3V, and these 3 voltages of 6.6V, what then obtain can calculate that by fitting formula obtaining corresponding Vg is 2.44V, 2.54V, 2.64V.Therefore the HCI stress test condition that obtains is by shown in the table (2).
Table (2)
| Vd(V) | Vg(V) |
| 6 | 2.44 |
| 6.3 | 2.539 |
| 6.6 | 2.638 |
Obtain 3 groups of HCI stress test conditions by table (2),, obtain the electricity degraded performance of said MOS device so that carry out the HCI stress test later on.
Compare with the HCI test MOS device method of traditional common; The present invention tests through 3 drain voltage Vd data that are lower than WV that original selected 3 drain stress voltage Vd stress test datas that are higher than WV are changed in the step 1; And scan pairing substrate current and grid voltage Isub-Vg curve under each drain voltage Vd that is lower than WV; Then, find substrate current maximal value Isubmax and the pairing grid voltage Vg of substrate current maximal value Isubmax value in each root substrate current and the grid voltage Isub-Vg curve through step 2, then; Find pairing grid voltage Vg value under the different drain voltage Vd values through step 3; Thereby produce grid voltage and drain voltage Vg-Vd graph of a relation, then, can be through grid voltage and the drain voltage Vg-Vd graph of a relation in the step 3; Obtain fitting formula through linear function; At last, obtain HCI stress test condition so that carry out the HCI stress test later on, obtain the electricity degraded performance of said MOS device according to the fitting formula in the step 4.This shows; Because the voltage that substrate current in the step 1 and grid voltage Isub-Vg curved scanning are loaded does not all surpass WV; For MOS device not damaged, therefore, above-mentioned MOS device still can be used as tested device and is used for later stress HCI test.Because the formulation of HCI stress test condition is reckoning and obtains, so need not to prepare the extra sample that is used to formulate the stress test condition.Therefore, the present invention only need provide the sample under the HCI test condition can carry out the formulation and the test of HCI stress test condition, has reduced sample, has practiced thrift testing cost.Simultaneously; In semiconductor fabrication process; The method that described definite hot carrier is injected the stress test condition not only can obtain the life-span that hot carrier is injected through the method for encapsulation utmost point test, and, also can obtain the life-span that hot carrier is injected through silicon wafer grade test; Therefore, can the actual test of strain need.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (7)
1. the method for a definite hot carrier injection stress test condition comprises the steps:
Step 1: select a MOS device; Said device MOS is carried out the hot carrier injection experiments; Under different drain voltages more than at least 3, measure the substrate current and the gate voltage curve of said MOS device respectively, wherein, said drain voltage is all smaller or equal to the WV of MOS device;
Step 2: for pairing substrate current of each drain voltage and gate voltage curve, find out the substrate current maximal value respectively, and read the pairing gate voltage values of substrate current maximal value;
Step 3: the pairing gate voltage values of substrate current maximal value under the different drain voltages that obtain according to step 2, produce grid voltage and drain voltage graph of a relation;
Step 4: grid voltage and drain voltage graph of a relation that step 3 obtains are used linear function fit, obtain fitting formula,
y＝Ax+B
Wherein, x is the drain voltage value, and y represents the gate voltage values of the MOS device of being tested that match draws, and A, B are constant;
Step 5: according to the fitting formula of step 4; Select for use at least 3 drain stress voltages as the substitution of x value; The y value that calculates respectively as the gate stress voltage value, and is constituted hot carrier respectively by each drain stress magnitude of voltage and corresponding gate stress voltage value thereof and injects the stress test condition.
2. definite hot carrier according to claim 1 is injected the method for stress test condition, it is characterized in that: a said MOS device is the tested device that hot carrier is injected stress test.
3. definite hot carrier according to claim 1 is injected the method for stress test condition, it is characterized in that: each drain voltage of a said MOS device be distributed with certain intervals.
4. definite hot carrier according to claim 1 is injected the method for stress test condition, and it is characterized in that: said each drain stress voltage all is higher than normal working voltage, and injects the drain voltage of stress test for hot carrier.
5. definite hot carrier according to claim 1 is injected the method for stress test condition, and it is characterized in that: said hot carrier injection into test is standard testing, carries out according to industry standard.
6. definite hot carrier according to claim 1 is injected the method for stress test condition, and it is characterized in that: said method can be used for silicon wafer grade test, or the package level test.
7. definite hot carrier according to claim 1 is injected the method for stress test condition, and it is characterized in that: a said MOS device is a nmos device, or the PMOS device.
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