CN102495352A - Multifunctional test circuit of integrated circuit stress degradation and test method thereof - Google Patents
Multifunctional test circuit of integrated circuit stress degradation and test method thereof Download PDFInfo
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- CN102495352A CN102495352A CN2011104434769A CN201110443476A CN102495352A CN 102495352 A CN102495352 A CN 102495352A CN 2011104434769 A CN2011104434769 A CN 2011104434769A CN 201110443476 A CN201110443476 A CN 201110443476A CN 102495352 A CN102495352 A CN 102495352A
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Abstract
The invention belongs to a integrated circuit reliability test technology field and especially relates to a multifunctional test circuit of integrated circuit stress degradation and a test method thereof. A core part of the test circuit takes an annular oscillator as a basis. Several auxiliary transistors, switch transistors and control terminals are added. By using the circuit and the method of the invention, a negative bias temperature instability, a positive bias temperature instability, hot hole injection or hot electron injection stress can be applied to pMOSFETs or nMOSFETs in a ring vibration inverter respectively; a ring oscillator is in a normal oscillation and stress oscillation state; the pMOSFETs or nMOSFETs of the inverter in the ring oscillator is in a measuring state of a charge pump. The degradation of the MOSFETs in the ring vibration inverter can be shown through changes of a ring oscillator oscillation frequency after the stress and can be shown through the changes of a CP current (Icpp or Icpn) of the pMOSFETs or nMOSFETs in the ring oscillator.
Description
Technical field
The invention belongs to the IC reliability technical field of measurement and test, be specifically related to test circuit and method of testing that a kind of integrated circuit stress is degenerated.
Background technology
It is two basic problems that influence complementary metal oxide semiconductor (CMOS) field effect transistor (CMOSFET) reliability that bias voltage temperature instability (BTI) and hot carrier are injected (HCI).For the nanoscale CMOSFETs that is made up of SiO2 or SiON gate medium, the Negative Bias Temperature Instability of pMOSFET (NBTI) is the main cause that influences device lifetime.But for the CMOSFETs that is made up of high-k gate dielectric, the positive bias temperature instability (PBTI) of nMOSFET and the HCI of p and nMOSFET have material impact to device reliability.
BTI and HCI degenerate and cause the drive current of MOSFETs to reduce, perhaps the increase of device delay.On the level of cmos circuit, above-mentioned degeneration can utilize the change of frequency of ring oscillator (ring shakes or RO) behind stress to characterize.Wherein the simplest a kind of metering circuit is to be core with single RO; Change in voltage through control end (OE) and power end; Make RO be in static stress, dynamic stress or normal oscillatory regime [V. Reddy et al., Impact of NBTI on Digital Circuit Reliability, IRPS respectively; 2002, p.248].Though the circuit that single RO constitutes is simple in structure, the measuring accuracy of change of frequency is not high.Improving improving one's methods of measuring accuracy is in circuit, to use two RO, and one of them RO does not add stress as reference; Another RO stress application, through the difference on the frequency (Δ f) of two RO of phase comparator measurement, thus degradation characteristics [the T. H. Kim of RO behind the acquisition stress; R. Persaud; And C. H. Kim, Silicon Odometer:An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits, IEEE JSSC vol.43; P.874,2008].
In aforesaid measuring method; Can combine dynamic stress to degenerate (comprising BTI and HCI simultaneously) and static stress degeneration (only comprising BTI) measurement result, distinguish the degeneration contribution of BTI and the HCI of CMOSFETs among the RO, but can't distinguish the PBTI degeneration of NBTI and the nMOSFETs of pMOSFETs among the CMOSFETs; Also can't distinguish HCI degeneration [the J. Keane et al. of pMOSFETs and nMOSFETs; On-chip reliability monitors for measuring circuit degradation, Microelectronics Reliability, vol. 50; P.1039,2010].Has mechanism of different because the PBTI of nMOSFETs degenerates and the NBTI of pMOSFETs degenerates; Degeneration or life model to circuit have different contributions; Therefore, in the degeneration of circuit is measured, distinguishing the PBTI degeneration of nMOSFETs and the NBTI degeneration of pMOSFETs needs the mission life of predicting integrated circuit.Similarly, in circuit, pMOSFETs and nMOSFETs are applied HCI stress independently, HCI degenerates and also needs behind the measurement stress.
The physical cause that the BTI of MOSFET and HCI degenerate is the generation of boundary defect between stress lower channel/medium (interface state) and the generation of medium inherent vice or electric charge.Because interface state, media defect and iunjected charge (oxide layer electric charge) that stress produces have different influences to electric properties of devices; Development can be distinguished the measuring method of the interface state, media defect and the iunjected charge that produce under the stress; For the degradation model of setting up MOS device and circuit, there is using value in the life-span of characterizing device and circuit.
The method of traditional measurement MOSFET interface state density is the method for charge pump (CP).This is a kind of externally measured method, and pumping signal is provided by the applying pulse generator, links drawing on the pad (Pad) of MOSFET to be measured through cable and probe.This method runs into very big difficulty when being used to measure the MOSFET of nanoscale.Because (W * L) too little, under driving pulse frequency commonly used (￡ MHz), cp is too little for the CP electric current I, can't measure for device area.If improve the driving pulse frequency, because the ghost effect of measuring systems such as cable, probe, the Icp of MOSFET can be covered by spur signal.For the CP that solves nanoscale MOSFET measures; Propose to measure on the sheet method [the R. Fernandez et al. of CP in the world; AC NBTI studied in the 1Hz-2GHz range on dedicated on-chip CMOS circuits, IEDM 2006, p.1039]; Promptly integrate measured device and the circuit that produces driving pulse, make the excitation frequency of CP can reach 2GHz.But (individual devices) that the measured device in the above-mentioned measuring method is still discrete, promptly measured device does not constitute any type of circuit.The stress of device is degenerated and can only be reflected with Icp through static characteristics such as IdVg, can't reflect as postponing through the dynamic perfromance of device, so can't contact directly together with the application of circuit.
Summary of the invention
The multifunctional testing circuit and the method for testing that the object of the present invention is to provide a kind of integrated circuit stress to degenerate.Utilize test circuit of the present invention and method of testing; Can apply NBTI, PBTI, HCI and dynamic stress to the crucial CMOSFETs in the test circuit respectively, utilize the frequency of annular oscillation circuit or the degradation characteristics of the crucial CMOSFETs of measure of the change under various stress of CP electric current I cp then.
The multifunctional testing circuit that integrated circuit stress provided by the invention is degenerated; Its core (core circuit) is the basis with a ring oscillator (RO_CP); Between every two-stage phase inverter of RO_CP; Insert one group of auxiliary pMOSFET and nMOSFET, the source of wherein auxiliary pMOSFET and nMOSFET meets noble potential Vdd1 and the electronegative potential Vss of RO_CP respectively.The leakage of every group of pMOSFET and nMOSFET connects together, and links to each other with the output of prime phase inverter and the input of back level phase inverter respectively with another switching transistor S2 through a switching transistor S1.The grid of all auxiliary pMOSFETs connects together, and receives first control end Vp; The grid of all auxiliary nMOSFETs connects together, and receives second control end Vn.The grid of all switching transistor S1 connects together, and receives the 3rd control end VS1; The grid of all switching transistor S2 connects together, and receives the 4th control end VS2.The substrate of pMOSFETs in all phase inverters of RO_CP connects together, and receives an outside link Icpp; The substrate of nMOSFETs in all phase inverters of RO_CP connects together, and receives another outside link Icpn.Switching transistor can be made up of single nMOSFET (switching transistor), also can be made up of the complementary switch circuit that two CMOSFETs form.All switching transistors are the I/O device, have thicker gate medium, and WV is higher than the WV of core circuit, the threshold value loss when avoiding the high level transmission.
The output of core circuit is connected to the input of first frequency divider, and the input of first impact damper is received in the output of first frequency divider, and the first external measuring junction OUT1 of test circuit is linked in the output of first impact damper.The hot end of first frequency divider and first impact damper is linked another high power end Vdd2 of circuit, and isolates with the high power end Vdd1 of core circuit.If the normal oscillation frequency of core circuit is f, the dynamic range of surveying instrument (like oscillograph or spectrum analyzer) is fd, then the Frequency Dividing Factor N of frequency divider>f/fd.
Except core circuit, test circuit also comprise one identical with the core circuit structure with reference to circuit RO_ref.Be connected to the input of second frequency divider with reference to the output of circuit, the input of second impact damper is received in the output of second frequency divider, and the second external measuring junction OUT2 of test circuit is linked in the output of second impact damper.The noble potential of the noble potential of second frequency divider and second impact damper and first frequency divider and first impact damper connects together, and receives another high power end Vdd2 of test circuit.If the normal oscillation frequency with reference to circuit is fref, the dynamic range of surveying instrument (like oscillograph or spectrum analyzer) is fd, then the Frequency Dividing Factor N of frequency divider>fref/fd.
Test circuit also comprises a phase comparator.Core circuit and two inputs of linking phase comparator with reference to the output of circuit, the output of phase comparator is connected to the input of the 3rd impact damper, and the 3rd external measuring junction OUT3 of test circuit linked in the output of the 3rd impact damper.The hot end of phase comparator and the 3rd impact damper and the hot end of other frequency divider and impact damper connect together, and receive another high power end Vdd2 of test circuit.Except that core circuit (RO_CP), the cold end of every other circuit connects together in the test circuit, receives another cold end GND of test circuit, and isolates with the cold end Vss of core circuit.
Also link the input end of all phase inverters among the core circuit RO_CP through some switching transistor S with reference to the output of circuit RO_ref.The grid of all switching transistor S connects together, and receives an external control end VS.Switch S can be made up of single nMOSFET (switching transistor), also can be made up of the complementary switch circuit that two CMOSFETs form.All switching transistors among the RO_ref are in conducting state all the time, and therefore the grid with all switching transistors among the RO_ref connects together, and receives another high power end Vdd3 of test circuit, and isolate with other two high power end Vdd1 and Vdd2.
Entire circuit has 15 external contact discs (Pad); The high power end Vdd1 that core circuit uses; The low power end Vss of a core circuit; One with reference to the common high power end Vdd2 that uses of circuit, frequency divider, impact damper and phase comparator, the low power end GND with reference to the common use of circuit, frequency divider, phase buffer and phase comparator, the control end Vdd3 with reference to all switches in the circuit; Three switch S, S1, the control end VS of S2, VS1, VS2; The control end Vp and the Vn of two pMOSFETs and nMOSFETs auxiliary transistor, the voltage of two CP applies and electric current (Icpp and Icpn) measuring junction, the output terminal OUT1 of three circuit, OUT2, OUT3.
In sum, the present invention proposes multifunctional testing circuit and the method for testing that a kind of integrated circuit stress is degenerated.The core of test circuit (core circuit) is the basis with ring oscillator (ring shakes or RO), additional auxiliary transistor, switching transistor and external control end.Through the conduction and cut-off state of control end control auxiliary transistor and the on off state of switching transistor; Can make core circuit be in normal vibration, stress oscillation respectively; Positive bias temperature instability (PBTI) stress that applies Negative Bias Temperature Instability (NBTI) stress, nMOSFETs of pMOSFETs; The hot hole of pMOSFETs or nMOSFETs injects (HHI or pHCI) or thermoelectron injects (HEI or nHCI) stress, and the charge pump of pMOSFETs or nMOSFETs (CP) measurement state.Except core circuit, test circuit also comprises one with reference to circuit, a phase comparator, two frequency dividers and three auxiliary circuits such as impact damper.Structure with reference to circuit is identical with core circuit, but the CMOSFETs in the circuit does not receive any stress, promptly follows the output frequency of core circuit under the normal oscillatory regime identical all the time with reference to the output frequency of circuit.In the stress degradation testing of core circuit, can be used to the frequency reference with reference to circuit, also can be used to the pulse generation source, measure with the CP that carries out CMOSFETs in the core circuit phase inverter.Therefore; The change of frequency that circuit of the present invention both can shake through ring also can change through the CP electric current of CMOSFETs, measures the stress degradation characteristics of CMOSFETs device and circuit; Comprise the dynamic stress degradation characteristics; The NBTI stress degradation characteristics of pMOSFETs, the PBTI stress degradation characteristics of nMOSFETs, the thermoelectron that the hot hole of pMOSFETs injects degradation characteristics and nMOSFETs injects degradation characteristics.
Description of drawings
Fig. 1 is the structural drawing of reliability testing circuit of the present invention.
Fig. 2 is the test circuit core: core circuit figure.
Fig. 3 be test circuit with reference to part: with reference to circuit diagram.
Fig. 4 is a kind of replacement circuit figure of switch.
Fig. 5 is a kind of circuit structure diagram of frequency divider.
Fig. 6 is a kind of circuit structure diagram of impact damper;
Fig. 7 is a kind of structural drawing of phase comparator.
Fig. 8 is a kind of domain framework of test circuit.
Fig. 9 is that test circuit is connected and arrangement plan with a kind of of peripheral instrument.
Figure 10 is the bias arrangement figure of core circuit RO_CP when being in normal oscillatory regime.
Figure 11 is the bias arrangement figure of the pMOSFETs in the core circuit RO_CP phase inverter when being in NBTI stress.
Figure 12 is the bias arrangement figure of the nMOSFETs in the core circuit RO_CP phase inverter when being in PBTI stress.
Figure 13 is the bias arrangement figure of the pMOSFETs in the core circuit RO_CP phase inverter when being in HCI stress.
Figure 14 is the bias arrangement figure of the nMOSFETs in the core circuit RO_CP phase inverter when being in HCI stress.
Figure 15 is the bias arrangement figure of the CMOSFETs in the core circuit RO_CP phase inverter when being in dynamic stress.
Figure 16 is the bias arrangement figure of the pMOSFETs in the core circuit RO_CP phase inverter when being in Icpp and measuring.
Figure 17 is the bias arrangement figure of the nMOSFETs in the core circuit RO_CP phase inverter when being in Icpn and measuring.
Label among the figure: 1 is ring oscillator RO_CP, and 3 is first frequency dividing circuit, and 4 is first buffer circuit, and 5 is with reference to circuit RO_ref, and 6 is second frequency dividing circuit, and 7 is second buffer circuit; 8 is phase comparator, and 9 is the 3rd buffer circuit; 11 are auxiliary pMOSFET, and 12 are auxiliary nMOSFET, and 13 is switching transistor S1, and 14 is switching transistor S2, and 51 is switching transistor S; 201 is the noble potential of ring oscillator RO_CP, and 202 is the electronegative potential Vss of RO_CP, and 203 is the first control end Vp, and 204 is the second control end Vn; 205 is the 3rd control end VS1, and 206 is the 4th control end VS2; 207 is outside link Icpp; 208 is outside link Icpn; 209 is externally measured end OUT1, and 210 is externally measured end OUT2; 211 is the 3rd externally measured end OUT3, and 212 are external control end VS.
Embodiment
Circuit of the present invention and method are used for the IC reliability test, particularly to the degradation testing of CMOSFETs under NBTI, PBTI, HCI and dynamic stress in the integrated circuit.The test parameter comprises the ring change of frequency that CMOSFETs stress is degenerated and caused in the phase inverter of shaking, and also comprises the CP electric current that CMOSFETs produces under stress.Integrated circuit is as shown in Figure 1; Have 15 outside contact discs (Pad); Be respectively the high power end Vdd1 of core circuit, the low power end Vss of core circuit is with reference to the common high power end Vdd2 that uses of circuit, frequency divider, impact damper and phase comparator; With reference to the common low power end GND that uses of circuit, frequency divider, impact damper and phase comparator; With reference to the control end Vdd3 of all switches in the circuit, the control end VS of switch S, S1, S2, VS1, VS2, the control end Vp and the Vn of pMOSFETs and nMOSFETs auxiliary transistor; Voltage (Vcpp and Vcpn) when CP measures applies and electric current (Icpp and Icpn) test lead the output terminal OUT1 of circuit, OUT2, OUT3.
Fig. 2 is by ring shakes, auxiliary transistor nMOSFETs and pMOSFETs, switching transistor S1 and S2 form core circuit RO_CP.Fig. 3 is identical with the core circuit structure with reference to circuit RO_ref.Fig. 4 is a kind of replacement circuit of switch.Fig. 5 is a kind of circuit structure diagram of frequency divider.Fig. 6 is a kind of circuit structure diagram of impact damper.Fig. 7 is a kind of circuit diagram of phase comparator.Fig. 8 is a kind of layout design framework of test circuit.
The peripheral instrument configuration of circuit connects as shown in Figure 9 during measurement.Wherein Vdd1, Vdd2, Vdd3, Vss, GND, VS, VS1, VS2, Vp, Vn connect external voltage source, can apply different voltages with different (or ground connection) according to different stress and measurement pattern.Icpp and Icpn connect the source measuring unit (SMU) in the analyzing parameters of semiconductor appearance, when applying voltage, measure electric current.OUT1, OUT2, optional oscillograph or the spectrum analyzer of connecing of OUT3.
Figure 10 is that core circuit is in the bias arrangement under the normal oscillatory regime; Be used to encircle the measurement of oscillation frequency of shaking: at Vdd1, Vp, the last WV Vdd0 that adds integrated circuit of Icpp; Vn, Icpn, Vss ground connection; VS1=VS2=VddI/O＞Vdd0+Vthn, and the switching transistor S among Fig. 1 is ended, i.e. VS ground connection.Under this configuration; Switching transistor S1 among core circuit Fig. 2, S2 are conductings, and auxiliary transistor pMOSFETs and nMOSFETs end, so core circuit is in normal oscillatory regime; Can measure through the oscillator signal OUT1 behind the frequency division by oscillograph; Therefrom can read output frequency fout, obtain the normal oscillation frequency f=N*fout of core circuit thus, wherein N is the divide ratio of frequency divider.
Figure 11 is that the pMOSFETs in the core circuit phase inverter is in the bias arrangement under the NBTI stress: on Vdd1, Icpp, Vp and Vn, add Vstress; VS1, Icpn, Vss ground connection; VS2=VddI/O＞Vstress+Vthn, and the switching transistor S among Fig. 1 is ended, i.e. VS ground connection.Under this configuration, the switching transistor S1 among core circuit Fig. 2 ends, the S2 conducting, and auxiliary transistor pMOSFETs is in cut-off state, and nMOSFETs is in conducting state.Therefore, the input of every grade of phase inverter is in electronegative potential 0 among the RO_CP, and the output of phase inverter is in noble potential Vstress, and promptly the pMOSFETs in the RO_CP phase inverter is in the NBTI stress state, and the nMOSFETs in the RO_CP phase inverter does not receive stress.
Figure 12 is that nMOSFETs is in the bias arrangement under the PBTI stress in the core circuit phase inverter: on Vdd1 and Icpp, add Vstress; VS1, Icpn, Vp, Vn and Vss ground connection; VS2=VddI/O＞Vstress+Vthn, and the switching transistor S among Fig. 1 is ended, i.e. VS ground connection.Under this configuration, the switching transistor S1 among core circuit Fig. 2 ends, switching transistor S2 conducting, and auxiliary transistor pMOSFETs is in conducting state, and nMOSFETs is in cut-off state.Therefore, the input of every grade of phase inverter is in noble potential Vstress among the RO_CP, and the output of phase inverter is in electronegative potential 0, and promptly the nMOSFETs in the RO_CP phase inverter is in the PBTI stress state, and the pMOSFETs in the RO_CP phase inverter does not receive stress.
Figure 13 is that pMOSFETs is in the bias arrangement under the HCI stress in the core circuit phase inverter: on Vdd1, Icpp, Vp and Vn, add Vstress; Icpn and Vss ground connection; VS1=VS2=VddI/O＞Vstress+Vthn, and the switch S among Fig. 1 is ended, i.e. VS ground connection.Under this configuration, the switching transistor S1 among core circuit Fig. 2, switching transistor S2 conducting, auxiliary transistor pMOSFETs is in cut-off state, and nMOSFETs is in conducting state.Therefore, among the RO_CP input and output of every grade of phase inverter all be in 0 and Vthn between current potential, promptly the pMOSFETs in the RO_CP phase inverter is in the HCI stress state, and the nMOSFETs in the RO_CP phase inverter does not receive stress.
Figure 14 is that nMOSFETs is in the bias arrangement under the HCI stress in the core circuit phase inverter: on Vdd1 and Icpp, add Vstress; Vp, Vn, Icpn and Vss ground connection; VS1=VS2=VddI/O＞Vstress+Vthn, and the switch S among Fig. 1 is ended, i.e. VS ground connection.Under this configuration, the switching transistor S1 among core circuit Fig. 2, switching transistor S2 conducting, auxiliary transistor pMOSFETs is in conducting state, and nMOSFETs is in cut-off state.Therefore, the input and output of every grade of phase inverter all are in the current potential between (Vstress+Vthp) and the Vstress among the RO_CP, and promptly the nMOSFETs in the RO_CP phase inverter is in the HCI stress state, and the pMOSFETs in the RO_CP phase inverter does not receive stress.
Figure 15 is that core circuit is in the bias arrangement under stress oscillation state or the dynamic stress: on Vdd1, Icpp and Vp, add Vstress; Vn, Icpn and Vss ground connection; VS1=VS2=VddI/O＞Vstress+Vthn, and the switch S among Fig. 1 is ended, i.e. VS ground connection.Under this configuration, switching transistor S1, switching transistor S2 among core circuit Fig. 2 are conductings, and auxiliary transistor pMOSFETs and nMOSFETs end, so core circuit is in the stress oscillation state, i.e. the dynamic stress state.
Figure 16 is the bias arrangement of the pMOSFETs in the core circuit phase inverter when being in CP and measuring: the WV Vdd0 that on Vdd2, adds integrated circuit; Vdd1 and Vss go up making alive Vdd ≈ Vdd0/2; Vp, Vn, VS2 and Icpn ground connection; VS1=Vdd3=VddI/O＞Vdd0+Vthn, and make the switch S conducting among Fig. 1, i.e. VS=VddI/O＞Vdd0+Vthn.Under this configuration; Switching transistor S1 conducting among core circuit Fig. 2, switching transistor S2 ends, auxiliary transistor pMOSFETs conducting; NMOSFETs ends; The grid of pMOSFETs provide driving pulse by RO_ref in the phase inverter, and source and drain voltage all be Vdd ≈ Vdd0/2, and substrate making alive Vcpp=Vdd ≈ can measure CP electric current I cpp in the time of Vdd0/2.
Figure 17 is the bias arrangement of the nMOSFETs in the core circuit phase inverter when being in CP and measuring: the WV Vdd0 that on Vdd2, Vp, Vn and Icpp, adds integrated circuit; Vdd1 and Vss go up making alive Vdd ≈ Vdd0/2; VS2 ground connection; VS1=Vdd3=VddI/O＞Vdd0+Vthn, and make the switch S conducting among Fig. 1, i.e. VS=VddI/O＞Vdd0+Vthn.Under this configuration; Switching transistor S1 conducting among core circuit Fig. 2, switching transistor S2 ends, and auxiliary transistor pMOSFETs ends; The nMOSFETs conducting; The grid of nMOSFETs provide driving pulse by RO_ref in the phase inverter, and source and drain voltage all be Vdd ≈ Vdd0/2, and substrate making alive Vcpn=Vdd ≈ can measure CP electric current I cpn in the time of Vdd0/2.
Utilize the NBTI stress degeneration step of pMOSFETs in the circuit measuring core circuit phase inverter of the present invention following:
(1), measures the output frequency fout of the novel circuit (Fresh circuit) do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider like Fig. 9 and shown in Figure 10.
(2) shown in figure 11, on core circuit, apply the NBTI stress of Vstress.
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime shown in Figure 10, and the oscillation frequency f1 of measurement core circuit (NBTI, tstress1).
(4) repeating step (2) and (3), the measurement core circuit the NBTI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (NBTI, tstress2), f3 (NBTI, tstress3) etc.
(5) change of frequency Δ f1 (the NBTI)=f1 of computation core circuit under NBTI stress (NBTI, tstress1)-f0, Δ f2 (NBTI)=f2 (NBTI, tstress2)-f0, Δ f3 (NBTI)=f3 (NBTI, tstress3)-f0 etc.
Utilize the PBTI stress degeneration step of nMOSFETs in the circuit measuring core circuit phase inverter of the present invention following:
(1), measures the output frequency fout of the novel circuit (Fresh circuit) do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider like Fig. 9 and shown in Figure 10.
(2) shown in figure 12, on core circuit, apply the PBTI stress of Vstress.
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime shown in Figure 10, and the oscillation frequency f1 of measurement core circuit (PBTI, tstress1).
(4) repeating step (2) and (3), the measurement core circuit the PBTI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (PBTI, tstress2), f3 (PBTI, tstress3) etc.
(5) change of frequency Δ f1 (the PBTI)=f1 of computation core circuit under PBTI stress (PBTI, tstress1)-f0, Δ f2 (PBTI)=f2 (PBTI, tstress2)-f0, Δ f3 (PBTI)=f3 (PBTI, tstress3)-f0 etc.
Utilize HCI (HHI) the stress degeneration step of pMOSFETs in the circuit measuring core circuit phase inverter of the present invention following:
(1), measures the output frequency fout of the novel circuit (Fresh circuit) do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider like Fig. 9 and shown in Figure 10.
(2) shown in figure 13, on core circuit, apply the HCI stress of Vstress.
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime shown in Figure 10, and the oscillation frequency f1 of measurement core circuit (HHI, tstress1).
(4) repeating step (2) and (3), the measurement core circuit the HHI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (HHI, tstress2), f3 (HHI, tstress3) etc.
(5) change of frequency Δ f1 (the HHI)=f1 of computation core circuit under HHI stress (HHI, tstress1)-f0, Δ f2 (HHI)=f2 (HHI, tstress2)-f0, Δ f3 (HHI)=f3 (HHI, tstress3)-f0 etc.
Utilize HCI (HEI) the stress degeneration step of nMOSFETs in the circuit measuring core circuit phase inverter of the present invention following:
(1), measures the output frequency fout of the novel circuit (Fresh circuit) do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider like Fig. 9 and shown in Figure 10.
(2) shown in figure 14, on core circuit, apply the HCI stress of Vstress.
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime shown in Figure 10, and the oscillation frequency f1 of measurement core circuit (HEI, tstress1).
(4) repeating step (2) and (3), the measurement core circuit the HEI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (HEI, tstress2), f3 (HEI, tstress3) etc.
(5) change of frequency Δ f1 (the HEI)=f1 of computation core circuit under HEI stress (HEI, tstress1)-f0, Δ f2 (HEI)=f2 (HEI, tstress2)-f0, Δ f3 (HEI)=f3 (HEI, tstress3)-f0 etc.
Utilize in the circuit measuring core circuit phase inverter of the present invention dynamic (Dynamic) stress degeneration step of CMOSFETs following:
(1), measures the output frequency fout of the novel circuit (Fresh circuit) do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider like Fig. 9 and shown in Figure 10.
(2) shown in figure 15, on core circuit, apply the dynamic stress of Vstress.
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime shown in Figure 10, and the oscillation frequency f1 of measurement core circuit (Dynamic, tstress1).
(4) repeating step (2) and (3), the measurement core circuit the following time of dynamic stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (Dynamic, tstress2), f3 (Dynamic, tstress3) etc.
(5) change of frequency Δ f1 (Dynamic)=f1 (Dynamic of computation core circuit under dynamic stress; Tstress1)-f0, Δ f2 (Dynamic)=f2 (Dynamic, tstress2)-f0; Δ f3 (Dynamic)=f3 (Dynamic, tstress3)-f0 etc.
Utilize the stress degeneration step of MOSFETs in the phase comparator measurement core circuit inverter in the circuit of the present invention following:
(1) like Figure 11,12,13, shown in 14 and 15, on core circuit, applies NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress respectively.
(2) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime shown in Figure 10, through OUT3 measurement core circuit with reference to the difference on the frequency Δ f1 of circuit RO_ref (Stress, tstress1)=fOUT3.
(3) repeating step (1) and (2); Through OUT3 measurement core circuit the following time of various stress be respectively tstress2, tstress3 etc. back with reference to the difference on the frequency Δ f2 (Stress of circuit RO_ref; Tstress2), Δ f3 (Stress, tstress3) etc.
Need to prove; Because circuit is domain mismatch or the influence of factor such as process deviation when making when being designed; Maybe be also unequal with reference to circuit RO_ref with the output frequency of the novel circuit RO_CP that does not add stress under normal oscillatory regime; But have certain deviation, can pass through output terminal OUT1, OUT2, this deviation of OUT3 measurement f0 this moment, and deduct (or adding) f0 on the difference on the frequency that in step (2), records.
Utilize the stress degeneration step of the CP electric current I cpp of pMOSFETs in the circuit measuring core circuit phase inverter of the present invention following:
(1), measures the CP electric current I cpp0 of the novel circuit (Fresh circuit) that does not add stress through the Icpp end like Fig. 9 and shown in Figure 16.
(2) like Figure 11,12,13, shown in 14 and 15, on core circuit, apply NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress respectively.
(3) behind the stress time tstress1, circuit arrangement is returned configuration shown in Figure 16, through Icpp end measure CP electric current I cpp1 (Stress, tstress1).
(4) repeating step (2) and (3), through the CP electric current I cpp2 of Icpp measurement core circuit after the following time of various stress is respectively tstress2, tstress3 etc. (Stress, tstress2), Icpp3 (Stress, tstress3) etc.
(5) CP electric current changes delta Icpp1 (Stress)=Icpp1 (Stress of computation core circuit under various stress; Tstress1)-Icpp0; Δ Icpp2 (Stress)=Icpp2 (Stress; Tstress2)-Icpp0, Δ Icpp3 (Stress)=Icpp3 (Stress, tstress3)-Icpp0 etc.
Utilize the stress degeneration step of the CP electric current I cpn of nMOSFETs in the circuit measuring core circuit phase inverter of the present invention following:
(1), measures the CP electric current I cpn0 of the novel circuit (Fresh circuit) that does not add stress through the Icpn end like Fig. 9 and shown in Figure 17.
(2) like Figure 11,12,13, shown in 14 and 15, on core circuit, apply NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress respectively.
(3) behind the stress time tstress1, circuit arrangement is returned configuration shown in Figure 17, through Icpn end measure CP electric current I cpn1 (Stress, tstress1).
(4) repeating step (2) and (3), through the CP electric current I cpn2 of Icpn measurement core circuit after the following time of various stress is respectively tstress2, tstress3 etc. (Stress, tstress2), Icpn3 (Stress, tstress3) etc.
(5) CP electric current changes delta Icpn1 (Stress)=Icpn1 (Stress of computation core circuit under various stress; Tstress1)-Icpn0; Δ Icpn2 (Stress)=Icpn2 (Stress; Tstress2)-Icpn0, Δ Icpn3 (Stress)=Icpn3 (Stress, tstress3)-Icpn0 etc.
Claims (4)
1. the multifunctional testing circuit that integrated circuit stress is degenerated is characterized in that comprising a core circuit, and this core circuit comprises a ring oscillator RO_CP (1); Between every two-stage phase inverter of ring oscillator RO_CP (1); Insert one group of auxiliary pMOSFET (11) and nMOSFET (12); The source of wherein auxiliary pMOSFETs and nMOSFETs is noble potential Vdd1 (201) and the electronegative potential Vss (202) of T-Ring shape oscillator RO_CP respectively; The leakage of every group of pMOSFET and nMOSFET connects together, and links to each other with the output of prime phase inverter and the input of back level phase inverter respectively with switching transistor S2 (14) through switching transistor S1 (13); The grid of all auxiliary pMOSFETs connects together, and receives the first control end Vp (203), and the grid of all auxiliary nMOSFETs connects together, and receives the second control end Vn (204); The grid of all switching transistor S1 connects together, and receives the 3rd control end VS1 (205), and the grid of all switching transistor S2 connects together, and receives the 4th control end VS2 (206); The substrate of pMOSFETs in all phase inverters of ring oscillator RO_CP connects together, and receives an outside link Icpp (207) separately; The substrate of nMOSFETs in all phase inverters of ring oscillator RO_CP connects together, and receives an outside link Icpn (208) separately; All switching transistors are the I/O device, and its WV is higher than the WV of core circuit, to avoid the high level threshold value loss in when transmission;
Described core circuit, also comprising a divide ratio is first frequency dividing circuit (3) and first buffer circuit (4) of N; The input of first frequency dividing circuit (3) is linked in the output of core circuit (1), and the input of first buffer circuit (4) is linked in the output of first frequency dividing circuit (3), and an externally measured end OUT1 (209) is linked in the output of first buffer circuit (4).
2. the multifunctional testing circuit that integrated circuit stress as claimed in claim 1 is degenerated; It is characterized in that test circuit also comprise one identical with the core circuit structure with reference to circuit RO_ref (5), second frequency dividing circuit (6) identical and second buffer circuit (7) identical with first buffer circuit with first frequency dividing circuit; Link the input of second frequency dividing circuit (6) with reference to the output of circuit RO_ref, the input of second buffer circuit (7) is linked in the output of second frequency dividing circuit (6), and another externally measured end OUT2 (210) is linked in the output of second buffer circuit (7); In addition, test circuit also comprises a phase comparator (8) and the 3rd buffer circuit (9); An input of phase comparator (8) is also linked in the output of core circuit (1); Also link another input of phase comparator (8) with reference to the output of circuit RO_ref (5); The input of the 3rd buffer circuit (9) is linked in the output of phase comparator (8), and the 3rd externally measured end OUT3 (211) linked in the output of the 3rd buffer circuit (9); With reference to each grade phase inverter among the ring oscillator RO_CP (1) is also linked in the output of circuit RO_ref (5) through some switching transistor S (51) input, the grid of all switching transistor S connect together, and receive external control end VS (212).
3. the multifunctional testing circuit that integrated circuit stress as claimed in claim 2 is degenerated is characterized in that:
In the described core circuit, as switch control end VS=0V, and as VS1=VS2=VddI/O＞Vdd+Vthn (threshold voltage of switching transistor), Vp=Vdd; Vn=Vss, Vcpp=Vdd, Vcpn=Vss; Vdd1=Vdd, when Vdd=Vdd0 was the WV of integrated circuit, switching transistor S ended; Switching transistor S1 and switching transistor S2 conducting, all p and n auxiliary transistor end, and ring oscillator RO_CP is in normal oscillatory regime;
Described with reference among the circuit RO_ref (5); Work as Vdd2=Vdd; Vdd3=VddI/O＞Vdd+Vthn when Vdd=Vdd0 is the WV of integrated circuit, does not receive stress with reference to all MOSFETs among the circuit RO_ref; And RO_ref is in normal oscillatory regime all the time, and promptly to catch up with the output frequency of stating circuit all the time identical for the output frequency of RO_ref;
In the described core circuit,, and work as VS1=0V, VS2=VddI/O＞Vdd+Vthn as switch control end VS=0V; Vp=Vn=Vdd, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd; When Vdd=Vstress＞Vdd0 was stress voltage, switching transistor S and switching transistor S1 ended, switching transistor S2 conducting; The p auxiliary transistor ends, the conducting of n auxiliary transistor, and grid, source and the leakage of pMOSFETs are in Vss, Vdd and Vdd respectively in all phase inverters of RO_CP; The grid of corresponding nMOSFETs and source all are in Vss, and promptly the pMOSFETs in all phase inverters of RO_CP is in the stress state of Negative Bias Temperature Instability (NBTI), and corresponding nMOSFETs is in unstressed condition;
In the described core circuit,, and work as VS1=0V as switch control end VS=0V; VS2=VddI/O＞Vdd+Vthn, Vp=Vn=Vss, Vcpp=Vdd; Vcpn=Vss, Vdd1=Vdd is when Vdd=Vstress＞Vdd0 is stress voltage; Switching transistor S and switching transistor S1 end, switching transistor S2 conducting, the conducting of p auxiliary transistor; The n auxiliary transistor ends, and the grid of pMOSFETs and source all are in Vdd in all phase inverters of RO_CP, and the grid of corresponding nMOSFETs, source and drain electrode are in Vdd, Vss and Vss respectively; Be the stress state that the nMOSFETs of all phase inverters is in positive bias temperature instability (PBTI) among the RO_CP, and corresponding pMOSFETs is in unstressed condition;
In the described core circuit, as switch control end VS=0V, and as VS1=VS2=VddI/O＞Vdd+Vthn, Vp=Vn=Vdd; Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd is when Vdd=Vstress＞Vdd0 is stress voltage; Switching transistor S ends, switching transistor S1 and switching transistor S2 conducting, and the p auxiliary transistor ends; The conducting of n auxiliary transistor, the pMOSFETs of all phase inverters is in conducting state among the RO_CP, and grid and leak are in identical current potential; But corresponding nMOSFETs is in cut-off state, and promptly the pMOSFETs of all phase inverters is in the stress state that hot carrier is injected (pHCI) among the RO_CP, and corresponding nMOSFETs is in unstressed condition;
In the described core circuit, as switch control end VS=0V, and as VS1=VS2=VddI/O＞Vdd+Vthn, Vp=Vn=Vss; Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd is when Vdd=Vstress＞Vdd0 is stress voltage; Switching transistor S ends, switching transistor S1 and switching transistor S2 conducting, the conducting of p auxiliary transistor; The n auxiliary transistor ends, and the pMOSFETs of all phase inverters is in cut-off state among the RO_CP, but corresponding nMOSFETs is in conducting state; And grid and leak are in identical current potential, and promptly the nMOSFETs of all phase inverters is in the stress state that hot carrier is injected (nHCI) among the RO_CP, and corresponding pMOSFETs is in unstressed condition;
In the described core circuit, as switch control end VS=0V, and as VS1=VS2=VddI/O＞Vdd+Vthn, Vp=Vdd; Vn=Vss, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd; When Vdd=Vstress＞Vdd0 was stress voltage, switching transistor S ended, switching transistor S1 and switching transistor S2 conducting; P and n auxiliary transistor all end, and promptly RO_CP is in the stress oscillation state, or the CMOSFETs among the RO_CP is in the dynamic stress state;
In the described core circuit, as switch control end VS=VddI/O＞Vdd0+Vthn, and as VS1=VddI/O＞Vdd0+Vthn, VS2=0V; Vp=Vn=0V, Vcpp=Vdd, Vcpn=0V, Vdd1=Vss=Vdd; During Vdd ≈ Vdd0/2, switching transistor S and switching transistor S1 conducting, switching transistor S2 ends; The conducting of p auxiliary transistor, the n auxiliary transistor ends, and the pMOSFETs of all phase inverters is in charge pump (CP) test mode among the RO_CP; The grid that are pMOSFETs provide driving pulse by RO_ref, and source and drain voltage all are Vdd ≈ Vdd0/2, and substrate making alive Vcpp=Vdd ≈ can measure CP electric current I cpp in the time of Vdd0/2;
In the described core circuit, as switch control end VS=VddI/O＞Vdd0+Vthn, and as VS1=VddI/O＞Vdd0+Vthn, VS2=0V; Vp=Vn=Vdd0, Vcpp=Vdd0, Vcpn=Vdd, Vdd1=Vss=Vdd; During Vdd ≈ Vdd0/2, switching transistor S and switching transistor S1 conducting, switching transistor S2 ends; The p auxiliary transistor ends, the conducting of n auxiliary transistor, and the nMOSFETs of all phase inverters is in the CP test mode among the RO_CP; The grid that are nMOSFETs provide driving pulse by RO_ref, and source and drain voltage all are Vdd ≈ Vdd0/2, and substrate making alive Vcpn=Vdd ≈ can measure CP electric current I cpn in the time of Vdd0/2.
4. utilize test circuit as claimed in claim 3 to measure the method that integrated circuit stress is degenerated, it is characterized in that:
One, the NBTI stress degeneration step of pMOSFETs is following in the measurement core circuit inverter:
(1) measuring the novel circuit do not add stress through output terminal OUT1 is the output frequency fout of Fresh circuit, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider;
(2) on core circuit, apply the NBTI stress of Vstress;
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime, and the oscillation frequency f1 of measurement core circuit (NBTI, tstress1);
(4) repeating step (2) and (3), the measurement core circuit the NBTI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (NBTI, tstress2), f3 (NBTI, tstress3);
(5) change of frequency Δ f1 (the NBTI)=f1 of computation core circuit under NBTI stress (NBTI, tstress1)-f0, Δ f2 (NBTI)=f2 (NBTI, tstress2)-f0, Δ f3 (NBTI)=f3 (NBTI, tstress3)-f0;
Two, the PBTI stress degeneration step of nMOSFETs is following in the measurement core circuit inverter:
(1) measures the output frequency fout of the novel circuit do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider;
(2) on core circuit, apply the PBTI stress of Vstress;
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime, and the oscillation frequency f1 of measurement core circuit (PBTI, tstress1);
(4) repeating step (2) and (3), the measurement core circuit the PBTI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (PBTI, tstress2), f3 (PBTI, tstress3);
(5) change of frequency Δ f1 (the PBTI)=f1 of computation core circuit under PBTI stress (PBTI, tstress1)-f0, Δ f2 (PBTI)=f2 (PBTI, tstress2)-f0, Δ f3 (PBTI)=f3 (PBTI, tstress3)-f0;
Three, the HCI stress degeneration step of pMOSFETs is following in the measurement core circuit inverter:
(1), measures the output frequency fout of the novel circuit do not add stress, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider through output terminal OUT1;
(2) on core circuit, apply the HCI stress of Vstress;
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime, and the oscillation frequency f1 of measurement core circuit (HHI, tstress1);
(4) repeating step (2) and (3), the measurement core circuit the HHI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (HHI, tstress2), f3 (HHI, tstress3);
(5) change of frequency Δ f1 (the HHI)=f1 of computation core circuit under HHI stress (HHI, tstress1)-f0, Δ f2 (HHI)=f2 (HHI, tstress2)-f0, Δ f3 (HHI)=f3 (HHI, tstress3)-f0;
Four, the HCI stress degeneration step of nMOSFETs is following in the measurement core circuit inverter:
(1) measures the output frequency fout of the novel circuit do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider;
(2) on core circuit, apply the HCI stress of Vstress;
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime, and the oscillation frequency f1 of measurement core circuit (HEI, tstress1);
(4) repeating step (2) and (3), the measurement core circuit the HEI following time of stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (HEI, tstress2), f3 (HEI, tstress3);
(5) change of frequency Δ f1 (the HEI)=f1 of computation core circuit under HEI stress (HEI, tstress1)-f0, Δ f2 (HEI)=f2 (HEI, tstress2)-f0, Δ f3 (HEI)=f3 (HEI, tstress3)-f0;
Five, the dynamic stress degeneration step of CMOSFETs is following in the measurement core circuit inverter:
(1) measures the output frequency fout of the novel circuit do not add stress through output terminal OUT1, by the normal oscillation frequency f0 of the divide ratio N computation core circuit of output frequency fout and frequency divider;
(2) on core circuit, apply the dynamic stress of Vstress;
(3) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime, and the oscillation frequency f1 of measurement core circuit (Dynamic, tstress1);
(4) repeating step (2) and (3), the measurement core circuit the following time of dynamic stress be respectively tstress2, tstress3 etc. oscillation frequency f2 (Dynamic, tstress2), f3 (Dynamic, tstress3);
(5) change of frequency Δ f1 (Dynamic)=f1 (Dynamic of computation core circuit under dynamic stress; Tstress1)-f0, Δ f2 (Dynamic)=f2 (Dynamic, tstress2)-f0; Δ f3 (Dynamic)=f3 (Dynamic, tstress3)-f0;
Six, the stress degeneration step of MOSFETs is following in the another kind of measurement core circuit inverter:
(1) on core circuit, applies NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress respectively;
(2) behind the stress time tstress1, circuit arrangement is returned normal oscillatory regime, through OUT3 measurement core circuit with reference to the difference on the frequency Δ f1 of circuit RO_ref (Stress, tstress1)=fOUT3;
(3) repeating step (1) and (2); Through OUT3 measurement core circuit after the following time of various stress is respectively tstress2, tstress3 with difference on the frequency Δ f2 (Stress with reference to circuit RO_ref; Tstress2), Δ f3 (Stress, tstress3);
Seven, the stress degeneration step of the CP electric current I cpp of pMOSFETs is following in the measurement core circuit inverter:
(1) holds the CP electric current I cpp0 that measures the novel circuit that does not add stress through Icpp;
(2) on core circuit, apply NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress respectively;
(3) behind the stress time tstress1, circuit arrangement is returned the configuration of step (1), through Icpp end measure CP electric current I cpp1 (Stress, tstress1);
(4) repeating step (2) and (3), through the CP electric current I cpp2 of Icpp measurement core circuit after the following time of various stress is respectively tstress2, tstress3 (Stress, tstress2), Icpp3 (Stress, tstress3);
(5) CP electric current changes delta Icpp1 (Stress)=Icpp1 (Stress of computation core circuit under various stress; Tstress1)-Icpp0; Δ Icpp2 (Stress)=Icpp2 (Stress; Tstress2)-Icpp0, Δ Icpp3 (Stress)=Icpp3 (Stress, tstress3)-Icpp0;
Eight, the stress degeneration step of the CP electric current I cpn of nMOSFETs is following in the measurement core circuit inverter:
(1) holds the CP electric current I cpn0 that measures the novel circuit that does not add stress through Icpn;
(2) on core circuit, apply NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress respectively;
(3) behind the stress time tstress1, circuit arrangement is returned the configuration of step (1), through Icpn end measure CP electric current I cpn1 (Stress, tstress1);
(4) repeating step (2) and (3), through the CP electric current I cpn2 of Icpn measurement core circuit after the following time of various stress is respectively tstress2, tstress3 (Stress, tstress2), Icpn3 (Stress, tstress3);
(5) CP electric current changes delta Icpn1 (Stress)=Icpn1 (Stress of computation core circuit under various stress; Tstress1)-Icpn0; Δ Icpn2 (Stress)=Icpn2 (Stress; Tstress2)-Icpn0, Δ Icpn3 (Stress)=Icpn3 (Stress, tstress3)-Icpn0.
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